3D Stacked DRAM - Logic Verification Engineer
- Pay
- $140,000 per year
- Location
- San Jose, CA · On-site
- Job type
- Full-time
- Level
- Senior
- Experience
- 4+ years
- Education
- Bachelor's degree
- Listed
- Today
Skills & highlights for this role
- SystemVerilog
- UVM
- Functional verification of SoCs and digital IPs
- Verification plan development
- Custom UVM agent development
- Regression execution and debugging
- Code and functional coverage closure
- Written and verbal English communication
Also useful
- Third-party VIP integration
- DRAM or memory design knowledge
- 3D-stacked IC / DRAM-on-Logic experience
- Customer engagement with TSMC or Intel
- EDA vendor collaboration
Job Summary
To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the verification of digital logic blocks. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.
Responsibilities
- Lead advanced IP verification for 3D-stacked DRAM, enabling DRAM-on-Logic system configurations with customers
- Verify digital logic blocks for 3D-stacked DRAM peripherals and DFT features, co-designing logic dies with U.S.-based customers
- Build technical partnerships with key customers (TSMC, Intel) to address 3D-stacked DRAM and foundry technology needs
- Establish verification of service-ready IPs and supporting infrastructure for the IP business
- Collaborate with EDA vendors to develop the verification environment and ensure seamless IP integration in customer design flows
- Co-develop next-generation DRAM-on-Logic solutions with key customers to strengthen competitiveness and market position
Qualifications
- Bachelor's degree or higher in Electrical Engineering or a related discipline
- Experience in semiconductor design verification, including test planning, verification environment development, simulation, debugging, and coverage analysis
- 4+ years of relevant experience in the following areas:
- Performed functional verification of SoCs, in-house and third-party digital IPs, and mixed-signal designs using SystemVerilog and UVM
- Developed specification-driven verification plans, test scenarios, and functional coverage models
- Developed in-house SystemVerilog/UVM-based Verification IP (VIP), including UVM agents for new protocols and custom IP interfaces
- Evaluated, integrated, and utilized third-party VIP within UVM-based verification environments
- Executed regression tests, debugged test failures, and drove code and functional coverage closure through coverage analysis and targeted test development
- Hands-on experience in end-to-end development of custom UVM agents based on design specifications
- Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management
Benefits
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
Compensation
Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.
About SK hynix America
At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers.
With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.
- Work Model: Onsite
- Job Title: 3D Stacked DRAM - Logic Design Verification Engineer
- Office Location: San Jose, CA
- Job Type: Full-Time
- Work Model: Onsite
Equal opportunity and legal notices
SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.
In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying:
- E-Verify Participation Poster (Bilingual English & Spanish)
- IER Right to Work Poster (English)
- IER Right to Work Poster (Spanish)
From SK hynix's careers page, first listed on Rolev.ai on November 12, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the 3D Stacked DRAM - Logic Verification Engineer role at SK hynix?
The 3D Stacked DRAM - Logic Verification Engineer posting at SK hynix states compensation of $140,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on SK hynix's official career site.
Where is the 3D Stacked DRAM - Logic Verification Engineer job at SK hynix located?
This 3D Stacked DRAM - Logic Verification Engineer position at SK hynix is located in San Jose, CA (On-site). Always check SK hynix's application page for specific state eligibility or relocation policies.
What qualifications are required for 3D Stacked DRAM - Logic Verification Engineer at SK hynix?
For the 3D Stacked DRAM - Logic Verification Engineer role, SK hynix highlights 4+ years of relevant experience; a bachelor's degree; experience with SystemVerilog, UVM, Functional verification of SoCs and digital IPs, Verification plan development, Custom UVM agent development, Regression execution and debugging. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the 3D Stacked DRAM - Logic Verification Engineer position at SK hynix?
This listing links directly to SK hynix's Greenhouse application page. You can apply directly on SK hynix's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Greenhouse application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.