3D Stacked DRAM - Memory Design Engineer
- Location
- San Jose, CA
- Listed
- 30 days ago
Job Summary
To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.
Responsibilities
- Strengthen leadership in the DRAM-on-Logic era through optimized DRAM Die design and technical innovation.
- Co-design 3D-stacked DRAM Logic Dies and next-generation DRAM-on-Logic solutions with U.S.-based customers.
- Design circuits for 3D-stacked DRAM that meet internal and external specifications, including DRAM DFT implementation.
- Review specifications and define the architecture for 3D-stacked DRAM products.
- Improve design quality and yield throughout the 3D-stacked DRAM development phase.
- Enhance performance and ensure stable operation to meet strict customer requirements during product development.
- Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM challenges.
- Drive market competitiveness and service differentiation through sustained customer collaboration and technical leadership.
Qualifications
- Bachelor's degree or higher in Electrical Engineering or a related discipline with 4+ years of relevant experience.
- Development of DRAM and design DRAM circuit based on custom design methodology (using virtuoso [or similar tools], spice simulator).
- Experience reviewing DRAM specifications and architecture.
- Circuit design experience to meet internal and external requirements for DRAM products.
- Experience evaluating compliance with DRAM specifications through design analysis at the wafer levels test / package levels test / system level test.
- Experience in full custom + digital Co-design and PDN analysis.
- Experience in full custom-based logic foundry design.
- Expert in Python, and circuit simulators (HSPICE, PrimeSim, Spectre, etc.).
- Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.
Benefits
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
Compensation
Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.
About SK hynix America
At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers.
With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.
- Work Model: Onsite
- Job Title: 3D Stacked DRAM - Memory Design Engineer
- Office Location: San Jose, CA
- Job Type: Full-Time
- Work Model: Onsite
Equal opportunity and legal notices
SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.
In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying:
- E-Verify Participation Poster (Bilingual English & Spanish)
- IER Right to Work Poster (English)
- IER Right to Work Poster (Spanish)
From SK hynix's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
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Common questions
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This 3D Stacked DRAM - Memory Design Engineer position at SK hynix is located in San Jose, CA. Always check SK hynix's application page for specific state eligibility or relocation policies.
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