ASIC Architect
- Pay
- $160,000 – $280,000 per year
- Location
- Remote (US)
- Listed
- 10 days ago
About the role
We are seeking a highly skilled and visionary ASIC Architect to define, architect, and guide the development of next-generation, high-performance ASICs. As a key technical leader, you will translate high-level system requirements into detailed architectural specifications, balancing power, performance, and area (PPA) trade-offs.
What we need
You will work across teams to define the architecture for IP blocks, sub-systems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads.
Key Responsibilities
- Lead the creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs including high-speed interconnect fabric and IO protocols (Ethernet, PCIe, UCIe).
- Develop high-level performance models (using SystemC/TLM, C++, or Python) to analyze workload behaviors and validate architectural assumptions.
- Optimize chip-level and block-level architecture to meet stringent power, performance, and area goals.
- Partner with RTL design, verification, physical design, firmware, and software teams to ensure seamless implementation and validation.
- Drive architectural trade-off studies and lead design reviews.
- Define advanced power management strategies including DVFS, power domains, and clock gating.
- Mentor junior engineers and contribute to technical leadership across the organization.
Required Skills and Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
- 7+ years of experience in ASIC architecture, micro-architecture, or high-level design.
- Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling.
- Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies.
- Experience with industry-standard protocols such as Ethernet, PCIe or UAL.
- Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar.
- Experience with performance modeling and analysis tools.
Desired Skills
- Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Experience designing AI/ML accelerators or high-performance networking silicon.
- Proven record of shipping high-performance silicon from concept to tape-out.
- Familiarity with pre-silicon emulation platforms.
- Strong scripting skills (Python, Tcl, Perl) for automation.
- Excellent communication skills and ability to articulate complex architectural concepts.
- Proactive problem solver capable of working with minimal oversight.
- Strong leadership and mentorship capabilities
Compensation
Target base salary for this role is $160,000 - $280,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.
Agency Note
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
Who we are
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
From Delos Data Inc.'s careers page, first listed on Rolev.ai on October 30, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the ASIC Architect role at Delos Data Inc.?
The ASIC Architect posting at Delos Data Inc. states compensation of $160,000 – $280,000 per year. Final pay may depend on location, experience, and interview evaluation on Delos Data Inc.'s official career site.
Where is the ASIC Architect job at Delos Data Inc. located?
Yes, this ASIC Architect opening at Delos Data Inc. is listed as Remote (US). Always check Delos Data Inc.'s application page for specific state eligibility or relocation policies.
How do I apply for the ASIC Architect position at Delos Data Inc.?
This listing links directly to Delos Data Inc.'s Ashby application page. You can apply directly on Delos Data Inc.'s site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Ashby application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.