ASIC Chip Design Lead

Position Overview

We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.

This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.

Responsibilities

Hands-on RTL Development

• Write, review, and debug production-quality RTL in Verilog/SystemVerilog
• Own RTL blocks end-to-end from specification through signoff
• Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
• Perform detailed code reviews and set a high technical bar for RTL quality

Micro-Architecture Specification

• Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
• Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
• Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution

Physical-Design–Aware Design & Timing Closure

• Work closely with Physical Design to improve synthesis and place-and-route timing.
• Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
• Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements

Verification Collaboration & Debug

Partner with Design Verification to debug functional and performance issues:

• Review functional and code coverage and provide actionable feedback
• Own bugs from discovery through fix, validation, and closure
• Full-Chip Integration & Signoff
• Own full-chip RTL integration and block roll-up

• Run chip-level synthesis, define constraints, and close chip-level timing
• Deliver timing-clean netlists to Physical Design that meet performance targets

Execution Discipline & Technical Leadership

• Drive block- and chip-level design checklists as execution quality gates
• Review checklist status with designers and proactively push closure of open items
• Continuously refine design methodologies, checklists, and flows based on silicon learnings
• Lead by technical authority and hands-on execution rather than coordination alone

Qualifications

• Strong hands-on experience with RTL design and micro-architecture
• Proven experience with full-chip integration and timing closure
• Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
• Deep understanding of synthesis, static timing analysis, and physical-design collaboration
• Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
• Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
• Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have

• Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
• Hands-on experience defining and refining SDC constraints and improving post-layout timing
• Knowledge of high-performance networking architectures and Ethernet-based systems
• Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
• Experience with chiplet-based system design

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

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