ASIC Design Engineer – Fabric/Interconnect
- Location
- Austin, TX · On-site
- Job type
- Full-time
- Level
- Mid-level
- Education
- Bachelor's degree
- Listed
- 14 days ago
Skills & highlights for this role
- RTL development
- On-chip interconnect architectures
- NoC topologies
- Crossbars
- Arbitration
- Coherent and non-coherent fabrics
- Memory hierarchy
- Synthesis
- Static timing analysis (STA)
- Functional verification
- Scripting
Also useful
- Cache coherency protocols (MESI, MOESI, directory-based coherence)
- High-volume low-power SoC delivery
- Lint
- Clock domain crossing (CDC)
- Synthesis tools
- Cross-functional collaboration
- Strong interpersonal skills
- Highly organized and schedule-driven
Summary
At Apple, phenomenal ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s best-in-class chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC.
This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design. Our position requires knowledge of interconnect fabrics and system memory hierarchy
About the role
- Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC with good understanding of on-chip interconnect architectures (NoC topologies, crossbars, arbitration).
- Own all aspects of RTL development design, templating, scripting and RTL generation.
- Work and collaborate with other designers in the group to deliver results.
- Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block.
- Work with front-end synthesis/STA teams to ensure timing for the block is met.
- Work with power/performance and functional verification team to ensure high quality of the block.
- Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process
Minimum Qualifications
Minimum of BS + 0 years relevant industry experience.
Preferred Qualifications
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy.
- A consistent track record of delivering large, sophisticated designs in high volume production for low power applications
- Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time
- Strong interpersonal skills, as the candidate will work with diverse groups within the company
- Self-starter, highly motivated, highly organized, and schedule driven
- Familiarity with all front-end tools including lint, CDC, synthesis
From Apple's careers page, first listed on Rolev.ai on October 27, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
Rolev.ai is a job search and application tool for US job seekers. For this ASIC Design Engineer – Fabric/Interconnect role at Apple, it shows how your resume fits, tailors your resume to the posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Common questions
Where is the ASIC Design Engineer – Fabric/Interconnect job at Apple located?
This ASIC Design Engineer – Fabric/Interconnect position at Apple is located in Austin, TX (On-site). Always check Apple's application page for specific state eligibility or relocation policies.
What qualifications are required for ASIC Design Engineer – Fabric/Interconnect at Apple?
For the ASIC Design Engineer – Fabric/Interconnect role, Apple highlights a bachelor's degree; experience with RTL development, On-chip interconnect architectures, NoC topologies, Crossbars, Arbitration, Coherent and non-coherent fabrics. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the ASIC Design Engineer – Fabric/Interconnect position at Apple?
This listing links directly to Apple's application page. You can apply directly on Apple's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.