ASIC Emulation and Verification Engineer

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About the role

Job Title: ASIC Emulation & Verification Engineer (Palladium Specialist)

Job Summary

We are seeking an experienced ASIC Emulation and Verification Engineer to bridge the gap between simulation and hardware acceleration. Your primary responsibility will be bringing up complex ASIC IP and SoC designs on Cadence Palladium emulation platforms, converting the RTL database into emulation-ready models, and executing high-speed hardware acceleration. Additionally, you will support the core pre-silicon team by performing standard UVM-based simulation, verification closure, and debugging tasks.

Key Responsibilities

• Palladium Emulation & Bring-up: Compile, synthesize, and map complex RTL databases onto Cadence Palladium hardware acceleration systems. Resolve compilation errors, manage clocking/memory overrides, and successfully bring up full-chip and sub-system emulation models.
• Firmware Co-Verification: Partner closely with firmware engineering teams to accelerate early FW bring-up on the Palladium platform. Provide hardware models, map memory spaces, and configure virtual debuggers (like JTAG) to allow teams to boot low-level bootloaders, drivers, and operating systems well before physical silicon is available.
• Standard Simulation Verification: Perform traditional pre-silicon verification tasks using SystemVerilog and UVM. Author test cases, develop monitors/checkers, and debug RTL anomalies using waveform viewers.
• Debug & Triage: Diagnose complex hardware, testbench, and environment issues on Palladium using advanced hardware-debugging features. Root-cause failures across both simulation and emulation environments.
• Infrastructure & Automation: Build and maintain automated scripts to seamlessly compile the RTL database and launch Palladium regressions. Manage database hand-offs between design release teams and the emulation environment.
• Minimum Qualifications
• Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 8 years of hardware description or verification experience.
• OR Master's Degree in a related field with a minimum of 6 years of relevant experience.

Preferred Skillsets & Technical Knowledge

• Emulation Platforms: Deep hands-on experience with the Cadence Palladium enterprise emulation platform (e.g., Palladium Z1/Z2 or newer systems).
• Front-End Flows: Strong proficiency in hardware description languages (Verilog / SystemVerilog) and hardware synthesis concepts for emulation mapping.
• Verification Methodologies: Proven experience with UVM (Universal Verification Methodology) simulation frameworks, assertion-based testing (SVA), and metric-driven coverage closure.
• Scripting & Tool Automation: Expertise in Python, Perl, Bash, or Tcl to parse log files, automate compiler tools, and manage massive regression databases.
• Hardware Architecture: Solid understanding of AMBA subsystem protocols (AXI, AHB, APB) and processor interfaces to safely configure memory and clock domains inside the emulator.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.