ASIC RTL Design Engineer, Ethernet IP & SoC Integration, SI Hardware

Asic Rtl

Design Engineer, Ethernet IP & SoC Integration, SI Hardware | Tesla (Tesla SI)

Location: Palo Alto, California | Req ID: 258189 | Job Type: Full-time

What to Expect

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities.

A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance.

By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

In this specialized role, you will focus on Ethernet IP integration, SoC clocking and reset architectures, and high-performance data paths within our custom ASICs. This role is located in Palo Alto, CA or Austin, TX. You will work closely with cross-functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in SI applications.

Candidates are expected to implement and document microarchitecture specifications tailored to networking and SoC integration, define system-level functional requirements for high-speed data handling, and deliver high-quality RTL designs optimized for SI workloads.

What You'll Do

• Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high-throughput data transfer in SI hardware systems
• Develop and optimize SoC clocking architectures, including multi-domain clock distribution, synchronization, and power-efficient clock gating techniques
• Architect and implement SoC reset mechanisms, including synchronous/asynchronous resets, reset domain crossing, and fault-tolerant recovery strategies
• Optimize high-performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines
• Integrate third-party IPs, such as Ethernet controllers and high-speed serdes, while managing interface protocols like AXI for efficient data movement
• Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking-focused subsystems
• Perform synthesis, timing analysis, and power optimization to meet aggressive performance targets in high-speed protocols
• Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations
• Document designs, specifications, and integration guidelines to support team collaboration and future iterations
• Participate in design reviews, code reviews, and contribute to overall ASIC development flows for SI hardware

What You'll Bring

• Degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience
• 3+ years of experience in ASIC RTL design using Verilog or SystemVerilog
• Strong knowledge of Ethernet protocols (e.g., 10G/25G/100G Ethernet, MAC/PHY layers, and IEEE standards)
• Expertise in high-speed protocols, including PCIe, SerDes, or similar interfaces for data-intensive applications
• Solid understanding of networking concepts, such as switching, routing, QoS, and packet buffering
• Hands-on experience with DMA controllers and high-performance memory access in SoC environments
• Proven track record in designing high-performance RTL for compute-intensive or data-heavy systems, with emphasis on pipelining and parallelism
• Proficiency with AXI/AMBA bus protocols for on-chip interconnects and IP integration
• In-depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi-clock domain handling
• Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains

Benefits

Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:

• Medical plans > plan options with $0 payroll deduction
• Family-building, fertility, adoption and surrogacy benefits
• Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
• Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
• Healthcare and Dependent Care Flexible Spending Accounts (FSA)
• 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
• Company paid Basic Life, AD&D
• Short-term and long-term disability insurance (90 day waiting period)
• Employee Assistance Program
• Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
• Back-up childcare and parenting support resources
• Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
• Weight Loss and Tobacco Cessation Programs
• Tesla Babies program
• Commuter benefits
• Employee discounts and perks program
• Earned Wage Access: Real-time pay access paid daily, subject to eligibility and schedule (applicable for below Sr. Managers levels)

Expected Compensation$128,000 - $312,000/annual salary + cash and stock awards + benefitsPay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position may also include other elements dependent on the position offered. Details of participation in these benefit plans will be provided if an employee receives an offer of employment.