CPU Subsystems RTL Design Engineer, SI Hardware

About the role

• CPU Subsystems RTL Design Engineer, SI Hardware | Tesla (Tesla SI)
• Location: Palo Alto, California | Req ID: 282804 | Job Type: Full-time
• What to Expect

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla's machine learning capabilities.

A key part of this effort is Tesla's next-generation SI accelerator chip, built to run massive neural networks efficiently at the edge. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD) and Tesla's humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance.

By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

In this role, you will own CPU subsystem integration, cache-coherent interconnect architecture, and SoC-level debug and trace infrastructure within our custom ASICs. You will work closely with cross-functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in SI applications.

You are expected to define and document microarchitecture specifications for CPU and interconnect integration, set system-level functional requirements for coherent memory traffic, and deliver high-quality RTL designs optimized for SI workloads.

What You'll Do

• Own end-to-end integration of ARM Cortex-A class CPU clusters (Armv8-A / Armv9-A) into custom SI SoCs, including cluster configuration, memory map definition, and boot architecture
• Architect and integrate the interrupt subsystem, including GIC (GICv3/GICv4) configuration, LPI/ITS support, message-signaled interrupts, and interrupt routing and affinity across cores
• Define and implement CPU cluster harvesting for yield recovery, including fuse-based core/cluster disable, boot-time configuration of active core sets, and correct enumeration of harvested topologies to interconnect, GIC, and debug infrastructure
• Design and implement RTL for coherent interconnect integration, ensuring correct and high-performance CHI or ACE/ACE-Lite connectivity between CPU clusters, accelerators, and memory subsystems
• Implement and validate CoreSight debug and trace infrastructure, including CTI/CTM cross-triggering, ETM/ETB/TMC trace paths, timestamping, and APB debug access
• Optimize CPU-to-memory and CPU-to-accelerator data paths for latency, bandwidth, and coherency overhead, including snoop filter sizing, cache maintenance flows, and DMA interaction
• Develop and optimize SoC clocking architectures for CPU subsystems, including multi-domain clock distribution, DVFS support, synchronization, and power-efficient clock gating
• Architect and implement reset and power-domain sequencing for CPU clusters, including core power-down/warm reset flows, reset domain crossing, and fault-tolerant recovery
• Partner with architecture, firmware, and verification teams to define and refine CPU subsystem microarchitecture, and represent the CPU subsystem in SoC-level architecture decisions
• Drive timing and power closure for the CPU complex in partnership with the physical design team, including RTL restructuring, pipeline adjustments, and hierarchy/floorplan feedback

What You'll Bring

• Degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience
• 7+ years of experience in ASIC RTL design using Verilog or SystemVerilog
• Strong hands-on experience integrating ARM Cortex-A series CPUs (Armv8-A and/or Armv9-A) and ARM interrupt controllers (GIC-400, GIC-600, GIC-700 or equivalent), including distributor/redistributor configuration and ITS into production SoCs.
• Expertise in cache coherency protocols, specifically AMBA CHI and/or ACE/ACE-Lite, including snoop transactions, coherency states, and ordering/barrier semantics
• Working knowledge of CoreSight debug architecture, including CTI/CTM cross-triggering, trace funnels and sinks, and debug authentication
• Hands-on experience with PLLs, clock dividers, glitch-free clock muxing, and clock gating to generate and manage the multiple clocks required by a CPU subsystem, including support for DVFS schemes
• Familiarity with UPF-based low-power design flows, including power domain partitioning for CPU clusters, isolation and level-shifter strategy, retention, and power state tables
• In-depth knowledge of multi-clock domain handling and clock domain crossing
• Experience with SoC reset and power-domain architectures, reset sequencing, and safe reset propagation across domains

Benefits

Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire:

• Medical plans > plan options with $0 payroll deduction
• Family-building, fertility, adoption and surrogacy benefits
• Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
• Company Paid (Health Savings Accounts) HSA Contribution when enrolled in the High-Deductible medical plan with HSA
• Healthcare and Dependent Care Flexible Spending Accounts (FSA)
• 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
• Company paid Basic Life, AD&D
• Short-term and long-term disability insurance (90 day waiting period)
• Employee Assistance Program
• Sick and Vacation time (Flex time for salary positions, Accrued hours for Hourly positions), and Paid Holidays
• Back-up childcare and parenting support resources
• Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
• Weight Loss and Tobacco Cessation Programs
• Tesla Babies program
• Commuter benefits
• Employee discounts and perks program
• Earned Wage Access: Real-time pay access paid daily, subject to eligibility and schedule (applicable for below Sr. Managers levels)

Expected Compensation$188,000 - $312,000/annual salary + cash and stock awards + benefitsPay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position may also include other elements dependent on the position offered. Details of participation in these benefit plans will be provided if an employee receives an offer of employment.