Custom ERC/Power-Intent Automation CAD Engineer

Summary

Interested in how Apple designs the world’s most advanced silicon? Want to write software that helps create the next generation of processors and enables the next astonishing Apple innovation? There's no telling what you could accomplish at Apple! We’re looking for an engineer who will bring passion for hardware and strong programming skills to our team of CAD engineers. You’ll develop, maintain and enhance custom analog power intent methodology and circuit ERC solutions for transistor level analysis on Analog, RF and mixed-signal designs.

In this role, you will have the opportunity to directly influence the circuit design on various technology nodes and develop CAD flows for circuit recognition, topology identification, netlist tracing, power domain interactions, and analyze electrical rule checks. Your contributions will be instrumental in the analog, mixed-signal, and RF circuit design teams.

You will lead and oversee efforts in developing and validating custom circuit checker flows, enhancing the custom design environment, validating checks, and conducting results analysis. As you collaborate with layout design, technology, and third-party EDA tool vendors, your expertise will be invaluable in driving innovation and ensuring the success of these initiatives.

The successful candidate will excel in dynamic, collaborative working environments and exhibit a hands-on, enthusiastic, self-motivated approach, with a strong drive to succeed in challenging settings. If you are eager to tackle challenges with innovative solutions, deliver exceptional user experiences, and pay meticulous attention to detail, this role may be the perfect fit for you. As a member of our team, your contributions will directly impact the experiences of millions of Apple customers in delivering state of the art processors to the wide range of Apple products.

About the role

In this highly visible role, your primary responsibilities will include

Developing innovative solutions on Circuit ERC (Electric Rules checks) or Power Intent analysis leveraging expertise on circuits and programming.

Actively involving yourself in supporting ERC/Power Intent on voltage domain interactions like – supply gating mechanisms, isolation controls, level shifting, switch supplies, virtual domain interactions, power integrity etc.

Closely collaborating with diverse design teams, including Custom Analog, Mixed-Signal, Digital, RF and more, to understand their needs and requirements on circuit ERC and power flows. Applying advanced techniques to address these requirements across multiple products and reduce duplicate design work.

Working in tandem with other domain in CAD, Power, Technology teams to validate their ML-based applications, implement enhancements, and evaluate external vendor packages and solutions from EDA (Electronic Design Automation) providers and open-source.

Minimum Qualifications

• Experience in Electric Rules Checks (ERC), circuit tracing and/or experience on custom power intent tools, flows and methodology.
• Relevant internship, research position or industry experience.

• Experience leading industry electrical engineering-focused software development project.
• Programming/scripting skills in Perl, Python, TCL, SKILL language, C++ or Shell.
• Ability to provide automations for rapid and dynamic design needs.

• Good written and verbal communication skills, and the ability to collaborate well with cross-functional teams.
• BS degree and 3+ years of relevant industry experience

Preferred Qualifications

Experience in understanding on the operating principles of common Analog, Digital/SRAM blocks, Spice Modeling in Nano CMOS technologies. Experience with custom Schematic/Layout tracing via SPICE/Open Access, power gating techniques, biasing, circuit topologies (power switches, level-shifter, iso), virtual/derived/multi-power domains, standard-cells would be helpful.

• Hands on experience with SVRF, TCL, Liberty/.lib, UPF - IEEE1801, CPF formats with exposure on power intent domain and methodology is a plus.
• Exposure to industry low power tools, Siemens Calibre PERC; Cadence Conformal LEC, Virtuoso Power Manager, Innovus; Synopsys Library compiler, VCLP, Low Power verification is desirable.
• Knowledge of Cadence Virtuoso Framework with experience on front end Schematic composer will helpful. Background in SPICE simulation, SOA, device operating conditions, and knowledge of Post-layout extraction is a plus.
• Ability to drive a software development team to develop novel and complex applications