Design Engineer - Timing Methodology
- Location
- USA-California-San Jose-1320 Ridder Park Drive
- Listed
- 11 days ago
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About the role
Broadcom's Timing Sign-Off group in Central Engineering is looking for an energetic and self-driven professional to join our team. Our group’s mission is to provide advanced timing sign-off methodologies to Broadcom’s chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
The candidate will participate and take ownership in Advanced Timing Sign-off methodology development and modeling for SOC and 3D/2.5D IC design. This includes complex studies and analysis of new concepts leading to design, development and improvement of existing and new solutions. The candidate should have experience in methodology development with deep knowledge of advanced silicon technologies, production testability and yield.
The candidate should have Tapeout experience in high volume / high yield complex SOCs at advanced technology nodes. The candidate will be working closely with other experts across the company in a fast paced project oriented agile environment.
The candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. The candidate will be expected to work across multiple facets of projects and juggle multiple responsibilities at the same time.
Responsibilities
- Develop and deploy timing signoff methodologies for advanced technology nodes.
- Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions.
- Participate & Lead in EDA flow development for Primetime, Tempus & Innovus.
Qualifications
- The minimum engineering experience required is typically a BS degree in EE/CS with 12+ years of industry experience, or an MS degree or Ph.D. degree in EE/CS with 10+ years of industry experience.
- Strong hands-on experience in Timing Signoff methodology development and ownership.
- Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
- Strong hands-on experience with statistical data analysis and modeling.
- Strong hands-on experience in silicon technologies, testability and yield.
- Strong hands-on experience with industry standard STA tools such as Primetime and Tempus.
- Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell and flow automation.
- Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.
- Strong analytical skills and extremely detail oriented, organized and methodical.
- Strong communication skills. Clear and concise.
- Strong multitasking and context switching skills.
- Optimistic yet pragmatic attitude.
- Demonstrable skills for quick ramp-up.
- Ability to stay calm under extreme pressure.
- Team player.
- Able to work with minimum supervision, handle ambiguity and drive problem solving to resolution autonomously.
Compensation and Benefits
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Equal opportunity and legal notices
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
From Broadcom's careers page, first listed on Rolev.ai on October 29, 2026. Rolev.ai is not the employer.
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Common questions
Where is the Design Engineer - Timing Methodology job at Broadcom located?
This Design Engineer - Timing Methodology position at Broadcom is located in USA-California-San Jose-1320 Ridder Park Drive. Always check Broadcom's application page for specific state eligibility or relocation policies.
How do I apply for the Design Engineer - Timing Methodology position at Broadcom?
This listing links directly to Broadcom's Workday application page. You can apply directly on Broadcom's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Workday application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.