Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

About the role

APPLE INC has the following available in Waltham, Massachusetts. Use both functional and formal verification to ensure bug-free delivery of features. Develop detailed test and coverage plans based on the microarchitecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment.

Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage. Develop verification plans for all features. Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under my care, and debug of the test failures.

Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage. Use EDA tools such as Cadence Xcelium for simulation, VManager for test plan development, Virtuoso for schematic viewing, Jasper Gold for formal verification and Verdi for waveform viewing and debugging. 40 hours/week.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $123,850- $175,200/yr and your base pay will depend on your skills, qualifications, experience, and location.

Pay & Benefits

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Computer Engineering or related field.
• Experience and/or education must include: Developing detailed test plans from design specifications
• Using SystemVerilog to verify high performance VLSI designs
• Using Universal Verification Methodology (UVM) to develop testbenches, tests, sequences, scoreboards, assertions, and coverage objects
• Setting up and executing regression suites
• Root-cause debugging of regression failures
• Analyzing functional and code coverage reports and closing coverage gaps
• Using Python, Perl, or Tcl to automate tasks
• Utilization of formal verification tools

Preferred Qualifications

N/A