Design Verification Engineer
- Location
- Austin, TX · On-site
- Job type
- Full-time
- Level
- Mid-level
- Education
- Bachelor's degree
- Listed
- 28 days ago
Skills & highlights for this role
- SystemVerilog/UVM
- Verilog
- Python
- assertion-based verification
- C++
Summary
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
About the role
APPLE INC has the following available in Austin, Texas. Ensure the quality of the SOC or an IP or subsystem. Review design and architecture specifications and work closely with design & micro-architecture teams. Develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches.
Communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. Work on one or several of the following types of IP such as Neural Engine hardware, DRAM subsystem, memory controller logic, Encode and Decode systems for ProRes and other codec formats such as VP9, AV1.
Hardware security, including cryptographic algorithm implementations, High-Speed IO standards such as PCI Express, DisplayPort, MIPI. Power management and fabric infrastructure, Memory cache management, Memory Management Unit, and Display Subsystem for variety of panels and product. 40 hours/week.
Minimum Qualifications
- Bachelor’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
- Experience and/or education must include: Implementing Computer Architecture to understand micro-architecture
Utilizing System Verilog/UVM to develop test-bench code and test-sequences:
- Using Python or Perl for scripting
- Using NCSIM and Xcelium for waveform debug
- Using C++ for writing CPU code
- Utilizing assertions writing to verify RTL
- Implementing Digital Design knowledge to understand design architecture
- Utilizing functional coverage and code coverage understanding to test coverage holes
Preferred Qualifications
n/a
From Apple's careers page, first listed on Rolev.ai on October 12, 2026. Rolev.ai is not the employer.
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Common questions
Where is the Design Verification Engineer job at Apple located?
This Design Verification Engineer position at Apple is located in Austin, TX (On-site). Always check Apple's application page for specific state eligibility or relocation policies.
What qualifications are required for Design Verification Engineer at Apple?
For the Design Verification Engineer role, Apple highlights a bachelor's degree; experience with SystemVerilog/UVM, Verilog, Python, assertion-based verification, C++. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Design Verification Engineer position at Apple?
This listing links directly to Apple's application page. You can apply directly on Apple's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.