Design Verification Engineer

Key Responsibilities

• Develop simulation tests, formal properties, reference models, and checkers for interconnect and chassis IP; learn to select and combine methods for the problem being verified
• Debug simulation failures and formal counterexamples, distinguish design issues from testbench or assumption errors, and work with the relevant owners to resolve them
• Translate specifications into verification plans and checks; review assumptions, coverage gaps, and proof results with the team, and take well-scoped features from initial bring-up through verification closure
• Participate in architecture and design discussions, use models and experiments to clarify behavior and tradeoffs, and contribute reviewed RTL or model changes in collaboration with their owners
• Build scripts and reusable tools for configuration generation, regression execution, and results analysis across generated designs
• Use AI-assisted tools in everyday coding, property development, and debugging; review generated work against design intent and validate it with tests and formal analysis rather than accepting the output at face value

What We're Looking For

You should demonstrate the following professional traits to be successful:

• Intellectual curiosity and a willingness to ask questions, incorporate feedback, and learn unfamiliar hardware and software concepts
• A methodical approach to problem-solving - one that distinguishes between what is expected, what is observed, and what needs to be investigated further
• A collaborative mindset with the ability to communicate clearly and work effectively with engineers across architecture, design, and verification disciplines

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field - with 6+ months of work or academic experience
• Foundation in digital logic, sequential circuits, and computer architecture, with the ability to read and reason about RTL
• Programming and algorithmic problem-solving skills, demonstrated in C/C++, Python, or an HDL through coursework, research, projects, or internships
• Experience explaining expected behavior, devise tests, and investigate unexpected results
• Hands-on use of AI-assisted development tools in coursework, research, or projects, including reviewing and testing the code they produce

Additional information

All minimum qualifications may be satisfied through internships, academic projects, coursework, or other practical experience.

Preferred Qualifications

• Coursework or project experience with RTL simulation, formal verification, SystemVerilog assertions, or UVM
• Familiarity with interconnects, cache and memory hierarchies, or protocols such as AXI, CHI, or PCIe
• Hands-on projects involving RTL design, FPGA implementation, hardware modeling, or hardware-software co-design
• Experience with Linux, Git, scripting, and automated build or test flows
• Experience building AI-assisted workflows for specification analysis, test or property generation, or debugging

Additional information

Preferred qualifications may also be satisfied through internships, academic projects, coursework, or other practical experience.

• Job Type: College Grad
• Shift: Shift 1 (United States of America)
• Primary Location: US, California, Santa Clara

Posting Statement

Position of Trust

N/A

Benefits

• We offer a total compensation package that ranks among the best in the industry.
• It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD

• The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
• Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
• Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.