Director of Buffer & Memory Subsystem Architecture
- Pay
- $250,000 – $300,000 per year
- Location
- San Jose, CA · On-site
- Job type
- Full-time
- Level
- Director
- Experience
- 8+ years
- Listed
- 31 days ago
Skills & highlights for this role
- memory controllers
- cache and prefetch architecture
- system performance modeling
Also useful
- SystemC
- HBM
- queueing models
Stated benefits & perks
- Health
- 401k match
Job Summary
As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF-xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.
Responsibilities
- Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment with headquarters and external partners.
- Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
- Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
- Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
- Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
- Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
- Define HBF Memory Architecture and Policies.
Qualifications
- 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms.
- Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization, with the ability to translate complex workload traces into architectural policies.
- Proven HW/SW co-design experience, including the ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
- Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components.
- Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software.
- Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.
Benefits
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
Compensation
Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets. Pay within the provided range varies by work location and may also depend on job-related skills and experience. Your Recruiter can share more about the specific salary range for the job location during the hiring process.
About SK hynix America
At SK hynix America, we are at the forefront of semiconductor innovation. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers.
With major investments in the U.S. and a leading position in the global AI revolution, we build the critical infrastructure of the digital landscape and remain committed to sustainable operations. We invite innovative minds to be part of our journey. Here, you will be part of a collaborative team pioneering the next generation of memory technologies, expanding our market footprint, and defining the future of computing.
- Work Model: Onsite
- Job Title: Director of Buffer & Memory Subsystem Architecture
- Office Location: San Jose, CA
- Job Type: Full-Time
- Work Model: Onsite
Equal opportunity and legal notices
SK hynix America is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information, or any other status protected under federal, state, or local applicable laws.
In compliance with federal law, SK hynix America also participates in the federal E-Verify program. Upon accepting an offer of employment, all newly hired individuals will be required to complete Form I-9, which includes verifying identity and legal authorization to work in the United States. Please review the official government posters detailing your rights and protections prior to applying:
- E-Verify Participation Poster (Bilingual English & Spanish)
- IER Right to Work Poster (English)
- IER Right to Work Poster (Spanish)
From SK hynix's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the Director of Buffer & Memory Subsystem Architecture role at SK hynix?
The Director of Buffer & Memory Subsystem Architecture posting at SK hynix states compensation of $250,000 – $300,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on SK hynix's official career site.
Where is the Director of Buffer & Memory Subsystem Architecture job at SK hynix located?
This Director of Buffer & Memory Subsystem Architecture position at SK hynix is located in San Jose, CA (On-site). Always check SK hynix's application page for specific state eligibility or relocation policies.
What qualifications are required for Director of Buffer & Memory Subsystem Architecture at SK hynix?
For the Director of Buffer & Memory Subsystem Architecture role, SK hynix highlights 8+ years of relevant experience; experience with memory controllers, cache and prefetch architecture, system performance modeling. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Director of Buffer & Memory Subsystem Architecture position at SK hynix?
This listing links directly to SK hynix's Greenhouse application page. You can apply directly on SK hynix's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Greenhouse application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.