DPU RAS and Debug Architect, Infrastructure Silicon
- Location
- Sunnyvale, CA · On-site
- Job type
- Full-time
- Level
- Lead / Staff
- Listed
- 28 days ago
Skills & highlights for this role
- SmartNIC/DPU architecture
- RAS architecture
- silicon debug
Also useful
- firmware co-design
- RTL collaboration
- post-silicon bring-up
About the role
Meta's Infrastructure Silicon organization designs custom silicon that powers our data center infrastructure — SmartNICs/IPUs/DPUs, AI accelerators, and networking ASICs.
We are looking for a Data Processing Unit (DPU) RAS and Debug Architect to define the reliability, availability, and serviceability architecture for our DPU ASICs.
You'll set FIT-rate targets from the intended usages and deployment models, define how errors are detected, corrected, and reported, and define the trace, debug, and performance-monitoring architecture that supports both post-silicon debug and software and firmware debugging.
You'll decide what belongs in hardware versus firmware versus software, define how the hardware presents itself to firmware and software, and work hand in hand with the firmware, driver, and RTL teams - carrying your designs from early path-finding through implementation and silicon bring-up.
From Meta's careers page, first listed on Rolev.ai on October 12, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
Rolev.ai is a job search and application tool for US job seekers. For this DPU RAS and Debug Architect, Infrastructure Silicon role at Meta, it shows how your resume fits, tailors your resume to the posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Similar roles
All Computer Hardware Engineer jobs- Ground Systems Computer Hardware Engineer 3/4 (AHT)Ngc · Colorado Springs, CO · $94.2k – $141k/yr
- Senior Staff Data Center Systems Engineer, R&DCrusoe · Denver, CO
- Senior or Staff Systems Engineer - Autonomous Vehicles (Atlanta, GA)Glydways · Atlanta, GA
- Sr. Core Integration Engineer (Starlink Mobile)SpaceX · Redmond, WA
- Staff Customer Qualification Engineer - 2276Kioxia · Folsom, CA · $115k – $192k/yr
- AI/ML Systems Engineer (2027 New College Graduate)GlobalFoundries · Richardson, TX
Common questions
Where is the DPU RAS and Debug Architect, Infrastructure Silicon job at Meta located?
This DPU RAS and Debug Architect, Infrastructure Silicon position at Meta is located in Sunnyvale, CA (On-site). Always check Meta's application page for specific state eligibility or relocation policies.
What qualifications are required for DPU RAS and Debug Architect, Infrastructure Silicon at Meta?
For the DPU RAS and Debug Architect, Infrastructure Silicon role, Meta highlights experience with SmartNIC/DPU architecture, RAS architecture, silicon debug. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the DPU RAS and Debug Architect, Infrastructure Silicon position at Meta?
This listing links directly to Meta's application page. You can apply directly on Meta's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.