Emulation Software Engineer

Key responsibilities

• Oversee SoC bring-up on emulation platforms; diagnose and resolve failing SoC/Processor tests.
• Develop innovative techniques to accelerate pre-silicon validation and software development.
• Provide support for various emulation environments, utilizing advanced emulation techniques including C/C++ DPI transactors, coverage analysis, and in-circuit emulation for high-speed protocols.
• Collaborate closely with teams across Design, DV, Silicon Validation, Performance, and Software, and partner with leading emulation vendors to enhance platform capabilities and troubleshoot complex issues.

Representative projects

• Develop high-performance software to capture debugging signals and create associated tooling to surface valuable insights for users.
• Implement a hybrid emulation environment using custom DPI-based streaming transactors.
• Create highly configurable chip-to-chip network models using emulation-efficient primitives.

You may be a good fit if you have

• Hands-on experience with emulation on platforms such as Palladium, Protium, Veloce, or Zebu, covering design bring-up, build flows, debugging, and performance tuning.
• Strong experience with C/C++ and Linux system development. Proficiency with SystemVerilog and Verilog, including DPI-based interfaces.
• Practical experience with scripting languages (i.e., Python) for automation.

Strong candidates may also have experience with

• Experience working with UVM verification environments.
• Background in design verification, DFT, and testbench modeling.
• Familiarity with waveform debug tools such as Verdi or SimVision.

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino

How we're different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.