Front-End CAD Engineer

Key responsibilities

• Own and manage Etched's front-end CAD environment including build flows, tool-specific flows and tool installation and configuration.
• Evaluate, deploy, and sustain front-end tools including but not limited to: RTL simulator, low power checker, static RTL checkers such as Lint, and CDC/RDC/SDC/DFT, and formal verification (both property and equivalence) checkers.
• Configure and manage project execution dashboard.

You may be a good fit if you have

• Experience developing and maintaining front-end IC design flows, including scripting and EDA tool configuration.
• Proficiency with (at least some) key verification tools: RTL simulation, static checks (lint/CDC/RDC), formal tools and low power tools.
• Ability to automate and optimize CAD workflows for chip design verification.
• Ability to interface with EDA vendors as well as internal users, identify the internal needs and priorities and bring in the relevant capabilities
• A can-do attitude and velocity of going from a problem sighting to a deployable solution.
• (Bonus) Hands-on RTL design experience, including ownership of a design block to validate CAD methodologies.

Strong candidates may also have experience

• Setting up and maintaining front-end IC design flows.
• Working directly with Synopsys and Cadence R&D, sales and field support teams.
• Working for other chip companies (i.e. Nvidia, Intel, AMD, Qualcomm, Marvell, Broadcom) or an internal chip team at a hyperscaler.

Benefits

• Full medical, dental, and vision packages, with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to Cupertino

How we're different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.