Full-Chip Physical Design Verification Engineer
- Pay
- $100,000 – $500,000 per year
- Location
- Austin, TX · Hybrid
- Job type
- Full-time
- Level
- Senior
- Experience
- 7+ years
- Education
- Bachelor's degree
- Listed
- 30 days ago
Skills & highlights for this role
- Calibre
- DRC
- LVS
- ESD planning
- IR drop analysis
Also useful
- Python
- TCL
- FinFET design
Who You Are
- A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
- A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
- A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
- A mentor and technical leader passionate about building efficient, manufacturable silicon.
What We Need
- BS/MS in Electrical/Electronics Engineering (or related) with 7-14 years of hands-on CPU/IP/SoC physical verification experience.
- Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
- Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
- Scripting proficiency in Python and TCL for automation and flow optimization.
What You Will Learn
- Advanced physical verification methodologies and flow optimization for next-generation SoCs.
- Integration and verification strategies for full-chip signoff across advanced process technologies.
- Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
- Leadership and mentoring opportunities in building scalable PV methodologies and automation.
Additional information
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).
These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
About Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You'll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we'd love to hear from you.
This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Equal opportunity and legal notices
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
From Tenstorrent's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
Rolev.ai is a job search and application tool for US job seekers. For this Full-Chip Physical Design Verification Engineer role at Tenstorrent, it shows how your resume fits, tailors your resume to the posting, and prepares the application for you to review.
See how you fit
Openings from employer career sites are ranked against your whole resume—and searchable inside Claude, ChatGPT, and Cursor via Rolev.ai MCP.
Tailor without inventing
Every change to your resume is checked against your original. New experience goes in only with your yes—zero fabricated claims.
Draft the full kit
Tailored and Full Match resumes, role-specific cover letters, and answers to employer screening questions are prepared in seconds.
1-Click Extension Autofill
The Chrome extension fills the employer's Greenhouse, Workday, Lever, or Ashby form in 1 click. You review it and press Submit.
Common questions
What is the salary for the Full-Chip Physical Design Verification Engineer role at Tenstorrent?
The Full-Chip Physical Design Verification Engineer posting at Tenstorrent states compensation of $100,000 – $500,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Tenstorrent's official career site.
Where is the Full-Chip Physical Design Verification Engineer job at Tenstorrent located?
This Full-Chip Physical Design Verification Engineer position at Tenstorrent is located in Austin, TX (Hybrid). Always check Tenstorrent's application page for specific state eligibility or relocation policies.
What qualifications are required for Full-Chip Physical Design Verification Engineer at Tenstorrent?
For the Full-Chip Physical Design Verification Engineer role, Tenstorrent highlights 7+ years of relevant experience; a bachelor's degree; experience with Calibre, DRC, LVS, ESD planning, IR drop analysis. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Full-Chip Physical Design Verification Engineer position at Tenstorrent?
This listing links directly to Tenstorrent's Greenhouse application page. You can apply directly on Tenstorrent's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Greenhouse application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.