IP Logic Design Engineer
- Pay
- $105,440 – $164,800 per year
- Location
- Rancho Cordova, CA · On-site
- Job type
- Full-time
- Level
- Mid-level
- Experience
- 7+ years
- Listed
- 30 days ago
Skills & highlights for this role
- Verilog
- SystemVerilog
- RTL design
- logic synthesis
- static timing analysis
Also useful
- 3D NAND flash memory
- lint tools
- CDC/RDC analysis
About the role
Join Solidigm's visionary Design Engineering Team as a 3D NAND IP Logic Design Engineer and help shape the future of memory technology.
Job responsibilities include, but not limited to: Architect, design, and verify logic and circuit blocks for 3D NAND flash memory components Define micro-architecture specifications, implement RTL in SystemVerilog, generate synthesis netlists with appropriate constraints, perform static timing analysis, resolve violations, implement ECOs, and drive design sign-off Develop and optimize microcode-based 3D NAND algorithms (read, program, erase, power-on) using proprietary instruction sets and compilers Contribute to next-gen 3D NAND architecture and pathfinding to improve density, die-size, performance, power, and cost Collaborate with pre-silicon verification teams to build unit-level test benches, implement SystemVerilog Assertions (SVAs), run full-chip RTL and gate-level simulation (GLS) regressions, and ensure functional and code coverage for various read-window-budget and customer features Review pre-silicon analog and mixed signal (AMS) simulations and post-silicon microprobe waveforms to conduct power & performance modeling and ensure the functionality of various digital & analog blocks Partner with product engineering and technology development teams to define Read-Window-Budget (RWB) features and develop Design for Testability (DFT) methods that reduce test time and cost while improving quality Support post-silicon debug and failure analysis across multiple configurations
Qualifications & Requirements
MS in electrical or computer engineering with 7+ years of experience, or BS with 9+ years of experience Proven expertise in Verilog and SystemVerilog, with deep understanding of ASIC design flow: RTL design, logic synthesis, STA, ECO Experience with lint tools, CDC/RDC analysis, and timing constraints Strong background in design verification tools and automation scripting Prior experience in 3D NAND Flash Memory logic design is a plus Ability to work independently across pre- and post-silicon debug cycles
Additional Information
The compensation range for this role is $105,440 - $164,800. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location. Powered by SmartRecruiters - Candidate Privacy Policy
About the Company
Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up.
In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world.
At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds.
At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions.
You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm.
We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.
From Solidigm's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the IP Logic Design Engineer role at Solidigm?
The IP Logic Design Engineer posting at Solidigm states compensation of $105,440 – $164,800 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Solidigm's official career site.
Where is the IP Logic Design Engineer job at Solidigm located?
This IP Logic Design Engineer position at Solidigm is located in Rancho Cordova, CA (On-site). Always check Solidigm's application page for specific state eligibility or relocation policies.
What qualifications are required for IP Logic Design Engineer at Solidigm?
For the IP Logic Design Engineer role, Solidigm highlights 7+ years of relevant experience; experience with Verilog, SystemVerilog, RTL design, logic synthesis, static timing analysis. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the IP Logic Design Engineer position at Solidigm?
This listing links directly to Solidigm's SmartRecruiters application page. You can apply directly on Solidigm's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the SmartRecruiters application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.