Memory Architect

Normal Computing | Build with US

Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

The Role

Normal is building AI inference hardware based on our revolutionary new Thermo In-Memory Computing architecture and as Memory Architect you will lead the translation of these concepts from theory into silicon. You will have free reign to completely reimagine each element of a conventional memory; from the design and layout read/write paths, organization of memory arrays, to the development of a microarchitecture which seamlessly interleaves core memory operations with high performance compute. Ultimately, you will be responsible for delivering 100-1000× improvements in performance in AI inference.

You will report to the Director of Silicon Engineering and partner with scientists, microarchitects, physical design, and analog design engineers to implement a new standard cell library which combines existing digital compute primitives with Normal’s ThermoDRAM compute primitives. You will translate these new compute primitives into a highly performant Compute In-Memory System. You will own the technical relationship with major manufacturers from PDK acquisition through tapeout of test chips and production silicon.

This role requires a seasoned engineer with prior experience in memory technology but who understands that radical performance improvements require radical paradigm shifts.

What You Will Own

• Architecture for Processing-In-Memory: Define the memory requirements and floorplan that enable in-memory compute capability. This includes not only read/write paths to ALUs but also novel memory primitives. Specify the read/write circuitry row/column decoders that enable novel memory and in-memory compute operations.
• Internal Bandwidth and Data Movement: Architect the local and global datapaths, segmented buses and on-die fabrics that move data between memory arrays and logic.
• Power Grid and Reliability: Own power distribution, power budgets, thermal limits, redundancy, and ECC so that peak memory and compute performance can be extracted from the system without damaging retention or yield
• PDK and Fab Path: Own access to process design kits and design rules and assess the limits and potential of architectural modifications which can be supported by existing design rules. Drive tapeout plan starting with an upcoming shuttle through test-chip content, schedule, and bring-up.
• Primitive Device Library: Partner with our analog engineers who build and characterize the primitive device library (write circuits, drivers, multiplexers). Set requirements and ensure design choices drive architectural performance considerations.
• Memory Interfaces: Define how our custom memory product interfaces to external hosts including SERDES, PCIE, Ethernet, DDR5, LP6, or HBM-class interfaces, command-set extensions, and controller/timing implications that impact performance.
• Modeling and Validation: Oversee development of SPICE, analytical, and cycle-level models of performance, power, and yield. Partner with performance and machine learning engineers to ensure projected PPA improvements translate into workload level gains.

What Makes You a Great Fit

• Substantial experience in memory architecture or circuit design at a memory manufacturer or a memory-centric compute company.
• Deep understanding of memory array physics: 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability
• Hands-on experience with embedded memory or random access memory technology and PDKs with experience developing memory test chips through tapeout
• Fluency moving between Spice-level circuit behavior through architecture-level performance and power models with strong fundamentals in one or more programming language (e.g. Python, C, C++) for modeling and performance prediction
• Experience in RTL and SystemVerilog to model and optimize dataflow and specify compute block requirements
• Experience with different interface types including memory interfaces
• Excellent written and spoken communication skills

Bonus Points

• Experience with process-in-memory or near-memory compute
• Experience with non-volatile memory technology
• Experience with DRAM technology including eDRAM
• Major publications at ISSCC, VLSI, IEDM, ISCA or other major conferences
• Existing relationships with manufacturers