Mixed Signal IC Layout Engineer
- Pay
- $100,000 – $500,000 per year
- Location
- Santa Clara, CA (Remote)
- Job type
- Full-time
- Level
- Mid-level
- Experience
- 10+ years
- Listed
- 30 days ago
Skills & highlights for this role
- BSEE
- full-custom analog layout
- Cadence Virtuoso
- Calibre DRC/LVS
- FinFET process nodes
- PLL/ADC/DAC layout
Also useful
- Synopsys Custom Compiler
- Python
- SKILL scripting
Who you are
- An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).
- Proficient with Synopsys Custom Compiler or Cadence Virtuoso for custom layout, and Synopsys ICV or Siemens Calibre for physical verification (DRC, LVS, ERC, DFM, Antenna).
- Deep experience in CMOS/FinFET nodes (ideally TSMC or Samsung 12nm-2nm) with delivered silicon and a strong grasp of EM/IR, ESD, and latch-up in mixed-signal layouts.
- Detail-oriented and organized, able to own complex blocks independently and collaborate effectively with circuit designers; typically hold a BSEE (or equivalent experience) with ~10+ years in analog/mixed-signal layout.
What we need
- Execute full-custom analog/mixed-signal layout for key blocks (PLLs, VCOs, ADCs, DACs, LDOs, bandgaps, comparators, clock generators, high-speed I/Os) from schematics to manufacturable layouts.
- Develop optimized block and top-level floorplans, placement, and routing that balance area, parasitics, matching, congestion, and integration into our D2D PHY.
- Apply best-known layout practices and optimize parasitics (R/C), coupling, IR drop, and electromigration to meet precision, noise, timing, and power goals while closing DRC, LVS, ERC, DFM, and Antenna.
- Support post-layout extraction and simulation and, as a bonus, contribute layout methodology and automation/scripts (Python, Tcl, SKILL, etc.) to improve team-wide quality and productivity.
What you will learn
- Deep, hands-on experience with cutting-edge FinFET technologies (down to 2nm) and the nuances of mixed-signal layout at these nodes.
- How to integrate high-speed analog/mixed-signal IP into a complex D2D PHY, including interactions across digital, analog, and I/O domains.
- Advanced approaches for managing EM/IR, ESD, latch-up, and physical-verification closure in dense mixed-signal environments.
- How to influence and evolve layout flows, methodologies, and automation, shaping how the broader team delivers high-quality silicon.
Additional information
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).
These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
About Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. The role focuses on high quality, high-speed analog/mixed-signal blocks and their integration into larger SoCs.
This role is remote, based out of any in the United States.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Equal opportunity and legal notices
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
From Tenstorrent's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the Mixed Signal IC Layout Engineer role at Tenstorrent?
The Mixed Signal IC Layout Engineer posting at Tenstorrent states compensation of $100,000 – $500,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Tenstorrent's official career site.
Where is the Mixed Signal IC Layout Engineer job at Tenstorrent located?
Yes, this Mixed Signal IC Layout Engineer opening at Tenstorrent is listed as Santa Clara, CA (Remote). Always check Tenstorrent's application page for specific state eligibility or relocation policies.
What qualifications are required for Mixed Signal IC Layout Engineer at Tenstorrent?
For the Mixed Signal IC Layout Engineer role, Tenstorrent highlights 10+ years of relevant experience; experience with full-custom analog layout, Cadence Virtuoso, Calibre DRC/LVS, FinFET process nodes, PLL/ADC/DAC layout. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Mixed Signal IC Layout Engineer position at Tenstorrent?
This listing links directly to Tenstorrent's Greenhouse application page. You can apply directly on Tenstorrent's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Greenhouse application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.