ML Algorithm Mapping and Performance Engineer, Core ML

About the role

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

The Core ML team develops novel algorithms for efficient large-scale training and inference. We are looking for an engineer who can determine how these algorithms should be mapped to the Cerebras architecture, when they outperform competing approaches, and how their advantages change as models, workloads, and hardware systems scale.

You will combine analytical performance modeling, empirical benchmarking, and hands-on prototyping to characterize the efficiency frontiers of emerging ML algorithms. Your work will span kernel-level and end-to-end performance, helping the team reason about trade-offs among model quality, latency, throughput, memory, communication, and compute utilization.

This role will directly influence which research ideas Core ML pursues, how those ideas are implemented on current Cerebras systems, and which capabilities should be considered in future generations of hardware and software.

Responsibilities

• Build analytical and empirical performance models for state-of-the-art ML training and inference algorithms.
• Characterize asymptotic behavior and identify how algorithmic trade-offs change with model size, sequence length, batch size, parallelism, and hardware scale.
• Construct Pareto frontiers across model quality, latency, throughput, memory footprint, communication, and compute cost.
• Develop prototype implementations and benchmarks for the Cerebras WSE and relevant GPU or software baselines.
• Analyze system behavior to identify kernel, compiler, runtime, communication, and algorithmic bottlenecks.
• Evaluate emerging techniques in areas such as parallel token generation, diffusion and speculative decoding, attention, sparsity, mixture-of-experts, low-precision computation, and distributed training.
• Partner with researchers and kernel, compiler, runtime, inference, and architecture teams to recommend high-value implementation and co-design directions.
• Develop tools and visualizations that make performance projections, measurements, and design trade-offs understandable across engineering and research teams.
• Clearly communicate conclusions, assumptions, limitations, and recommendations through technical reports, presentations, and design reviews.

Skills & Qualifications

• Bachelor’s, Master’s, PhD, or equivalent practical experience in Computer Science, Computer Engineering, Electrical Engineering, Mathematics, or a related field.
• Strong foundation in computer architecture, parallel computing, and systems performance.
• Strong understanding of machine learning fundamentals and ML systems, including how model and algorithmic choices affect compute, memory, communication, accuracy, and scaling behavior.
• Experience with analytical performance modeling, algorithmic complexity analysis, benchmarking, or system simulation.
• Strong analytical and problem-solving skills, including the ability to reason from first principles about compute, memory, and communication costs.
• Proficiency in Python and comfort with C++.
• Experience profiling and debugging performance in an ML, HPC, CPU, GPU, or accelerator-based system.
• Ability to move between mathematical analysis, experimental validation, and practical engineering recommendations.

Preferred Skills & Qualifications

• Experience with roofline analysis, CPU or GPU simulators, kernel optimization, or hardware-software co-design.
• Familiarity with CUDA, Triton, PyTorch, JAX, or open-source LLM training and inference systems.
• Understanding of transformer internals, including attention variants, KV-cache strategies, model parallelism, sparsity, quantization, and parallel generation.
• Research publications, patents, or significant open-source contributions related to ML systems, computer architecture, or computational efficiency.
• Experience evaluating technology choices for future hardware or software architectures.