Performance Architect, CPU Cluster

Who You Are

• You have a strong foundation in CPU microarchitecture and performance, with an understanding of how cores, caches, interconnects, and memory systems interact.
• You enjoy using modeling, simulation, and workload analysis to understand cluster-level performance bottlenecks and scaling challenges.
• You're comfortable moving between detailed microarchitecture and broader system-level questions around latency, bandwidth, quality of service, utilization, and scalability.
• You're analytical and hands-on, with the ability to turn large amounts of performance data into clear architectural recommendations.
• You're a strong communicator who enjoys working across architecture, RTL, compiler, software, and system teams.

What We Need

• Analyze and optimize CPU cluster performance, including cache hierarchies, interconnects, coherence, and memory access behavior.
• Build and use performance models and simulation environments such as Gem5 or equivalent to evaluate architectural concepts and identify performance opportunities.
• Study real workloads to understand bottlenecks related to cache misses, coherence traffic, memory bandwidth, latency, contention, and core-to-core communication.
• Lead architectural tradeoff studies across performance, scalability, bandwidth, latency, power, and implementation complexity.
• Collaborate with CPU, cache, interconnect, memory, software, and system architects to translate performance analysis into concrete design decisions.

What You Will Learn

• How to architect, model, and optimize a multi-core CPU cluster from early performance exploration through implementation and silicon.
• How cache coherence, interconnects, memory hierarchy, and core architecture interact to determine overall system performance.
• How to model and reason about scaling across cores, including contention, bandwidth limits, latency, and workload behavior.
• How architectural decisions at the cluster level translate into real-world application performance.
• How Tenstorrent approaches scalable CPU and chiplet-based system architecture across compute, interconnect, and memory.

Additional information

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).

These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.

If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.