Physical Design Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

About the role

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Collaborate with the package and floorplan teams on pad ring, bump, and RDL designs; Perform various types of physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level; Interface with the CAD/Technology teams for flow bring up and validation; Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out; Support schedules and cross-functional engineering effort; Work with FE team to understand chip architecture and drive physical verification aspects early in design cycle.

Configure, review, and provide timely feedback on full chip DRC, LVS, PERC and other full chip physical verification analysis; Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support; Support partition owners with PnR activities, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR; and Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

Pay & Benefits

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.

2 years of experience with each of the following skills is required

• DRC debug--Review custom, analog, and digital physical design data using industry standard Design Rule Checking, e.g. Calibre DRC and provide guidance to design owners to resolve all violations.
• LVS debug--Review custom, analog, and digital physical design data using industry standard Layout Versus Schematic checks, e.g. Calibre LVS and provide guidance to design owners to resolve all mismatches.

Cmos

Layout Design--Design custom layout and routing to be used in product and test chips using industry standard tools, e.g. Cadence Virtuoso, including but not limited to bumps and RDL.

Experience and/or education must include

• PNR/APR implementation--Design auto Place And Route designs using industry standard PNR tools, e.g. Cadence Innovus.
• Tcl/Perl/Python script development--specify and code Tcl/Perl/Python scripts to facilitate the design, verification, and signoff of physical design data.

Preferred Qualifications

N/A