Physical Design Engineer - Synth, Senior

Role Overview

We're looking for a Senior Physical Design Engineer - Synth to own synthesis, timing convergence, and implementation readiness for key partitions across our AI accelerator roadmap.

This is a hands-on engineering role responsible for turning high-quality RTL into implementation-ready netlists, developing and maintaining timing constraints, and driving physical-aware optimization in close collaboration with RTL designers and backend implementation partners.

You will be a key technical link between architecture, RTL, verification, and physical implementation, working alongside senior technical leadership to strengthen and scale our synthesis methodology.

Key Responsibilities

Synthesis Execution & Methodology

• Own synthesis for assigned partitions and subsystems, delivering clean, high-QoR netlists on schedule.
• Contribute to the development and improvement of synthesis flows, including constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation.
• Help define and apply signoff criteria for synthesis deliverables.

Hands-On Synthesis & Constraint Development

• Run hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler (or equivalent).
• Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments.
• Track and continuously improve synthesis QoR for your blocks.

Timing Closure

• Drive logical timing closure for assigned partitions, optimizing across frequency, area, power, congestion, and wireability.
• Perform root-cause analysis of timing bottlenecks and contribute to chip-level timing budgets.
• Work with architecture and RTL teams to identify and resolve timing risks before physical implementation.

Physical-Aware Optimization

• Partner with backend implementation engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization, and logic restructuring.
• Give RTL teams actionable feedback so designs are implementation-friendly from the outset.

Cross-Functional Execution

• Collaborate with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.

Vendor Collaboration

• Work with external implementation partners to review QoR, timing, and area reports, and support constraint methodology and acceptance criteria.

AI-Enabled Engineering

• Apply AI tools to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.

Required Qualifications

• 8+ years of ASIC implementation experience, including at least two successful tapeouts.
• Strong hands-on proficiency in synthesis and flow development.
• Proven experience closing timing on complex, multi-million-gate designs.
• Deep working knowledge of Cadence Genus and/or Synopsys Design Compiler.
• Strong SDC expertise, including constraint development and MMMC environments.
• A solid grasp of RTL design principles and implementation-friendly coding practices.
• Hands-on experience with advanced process nodes (7nm and below preferred).
• Strong Tcl and Python scripting ability for automation and flow development.
• Excellent debugging and root-cause analysis skills.

Preferred Qualifications

• Experience with AI accelerators, CPUs, or GPUs.
• Experience at 5nm and below.
• Familiarity with LPDDR, PCIe, or SerDes interfaces.
• Exposure to chiplet-based architectures and multi-clock SoC designs.
• Experience mentoring junior engineers or leading synthesis for a subsystem.

Leveling & Scope

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. This job description is a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

What Success Looks Like

Within one year, this person will have delivered predictable timing closure and high-QoR netlists for their assigned partitions, reduced implementation iterations through strong constraints and early RTL feedback, and made meaningful contributions to a scalable synthesis methodology that supports future ASIC generations.

Compensation & Benefits

• The base salary range for this role is $200,000 - $300,000.
• These figures represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity and individual impact.

Benefits & Perks

We want you to do your best work and feel confident that you and your family are taken care of. That means comprehensive coverage, real time to rest, and support for your future.

Health and wellness

• Fully company-paid medical, dental, and vision insurance for you and your dependents
• Company-paid life and disability coverage, with voluntary options to add more
• Supplemental hospital, critical illness, and accident coverage available

Time off and flexibility

• Unlimited paid time off - we encourage everyone to truly unplug and recharge
• 13 paid company holidays
• Remote-first culture with a company-provided computer and home office setup

Compensation and future

• Competitive salary and equity
• 401(k) with company matching, eligible from day one

Visa Support

This position is open to candidates currently authorized to work in the U.S. We cannot provide new visa sponsorship for this role but are open to facilitating H-1B visa transfers for eligible candidates.