Physical Design Engineer - Timing Lead

Key Responsibilities

• Drive and develop Timing flows, methodology for state of the art finfet and multi patterning based technologies from scratch in Cadence Tempus or Synopsys Primetime.
• Own and drive timing convergence of IP, Subsystem and SOC blocks.
• Define timing margining, PVTRC corner definitions, extraction methodology, signoff timing to SYN/PNR correlation.
• Develop slew rate, glitch noise checks to ensure robust design quality.
• Develop custom timing checks as pertains to Efficients proprietary Ultra low power architecture.
• Work closely with RTL team, DFT and IP vendors to define and drive SDC constraints.
• Have an in-depth understanding of all collaterals for all hard and soft IPs used by the design.
• Partner with post-si products bring up team to ensure good pre-si to post-si correlation from a timing perspective.
• Work with 3rd party vendor resources and coordinate their work in the timing domain.
• Continuously work on improving flow consistency and efficiency in the context of multiple product type swim lanes.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Proven track record of delivering IP/SS (or SoC) STA sign-off for multiple tape-outs in 12nm or below process technologies.
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for STA/simulations (PT/Hspice) with hierarchical design and abstraction techniques
• Hands-on experience in timing convergence of high-frequency and low power designs.
• Expert knowledge of static timing analysis, defining constraints and exceptions, corners/voltage definitions and timing margining.
• Experience with low power implementation typical in industry and how timing convergence impacts power draw ensuring we are making optimal tradeoffs.
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications

• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign-off budgeting
• Knowledge of circuit design, device physics, deep sub-micron technology, and SOI technology and its implications to physical design
• Proficiency with industry-grade physical design flow and hands-on building CAD flow infrastructure for PD engineers.
• Definition of design constraints for static timing analysis (synthesis, pre/post-cts, sign-off) and corners/voltage definitions.
• Experience in integrating analog or mixed-signal macro on top-level design.

Pay and benefits

We offer a competitive base salary for this role, generally ranging from $180,000 to $260,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.