Principal ASIC Package Design Engineer

About the role

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger - helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.

The Role

We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.

Responsibilities

• Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
• Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
• Establish organizational package design standards, methodologies, and best practices.
• Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
• Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
• Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
• Manage relationships with external packaging vendors, substrate suppliers, and
• OSATs, including vendor qualification, capability assessment, contract negotiation, and performance/quality score carding to ensure roadmap and volume commitments are met.
• Drive material selection, substrate technology choices, and assembly process optimization.

Required Qualifications

• Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
• 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
• Proven experience delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors.
• Knowledge of packaging qualification and test methodologies.

Preferred Qualifications

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.
• Experience defining packaging strategy from early architecture through first silicon and volume ramp.
• Demonstrated history of building or scaling package design methodology within an organization.

Compensation and Benefits

• Base salary range for this role is $200,000 - $280,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.