Principal DFT Engineer (Silicon Engineering)

About the role

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide.

We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Responsibilities

• Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Run and debug non-timing and SDF annotated gate level simulations
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C+

Basic Qualifications

• Bachelor's degree in electrical engineering, computer engineering or computer science
• 10+ years of experience working with ASICs
• 10+ years of experience in scan insertion and DFT setup, integration and validation

Preferred Skills and Experience

• Leadership experience driving SOC DFT execution from concept through tapeout and product deployment
• RTL experience to understand, trace and debug RTL connectivity issues as they pertain to DFT
• Ability to solve complex problems including clock domain crossings and power optimization
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Familiar with advanced silicon process and technology nodes for high speed and low power consumption
• Strong implementation or integration of design blocks using Verilog/SystemVerilog
• Experience working with ATE testers and test teams

Additional Requirements

• Ability to work extended hours and weekends as needed to meet critical milestones

Itar Requirements

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.