Principal Digital Design Engineer
- Location
- Duluth, GA · On-site
- Job type
- Full-time
- Level
- Lead / Staff
- Experience
- 12+ years
- Education
- Bachelor's degree
- Listed
- 23 days ago
Skills & highlights for this role
- Verilog RTL
- ASIC design methodology
- static timing analysis
- formal verification
- DFT
Also useful
- ATPG
- gate-level simulation
- CDC/RDC checking
About the role
- Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit
- Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
- Apply clocking controls, FSM design, low power techniques, and high-speed design concepts
- Participate in design, architecture, and verification reviews
- Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking
- Create documentation targeting design, verification, and test teams
- Assist with the proposal, definition, documentation, and implementation of new features
- Mentor and train junior engineers and New College Grad engineers
Qualifications & Requirements
- Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 12+ years of experience
- 12+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow
- Experience in architecting digital designs and writing device-level or sub-system specifications.
- Fluent in Verilog RTL coding and ASIC design methodology
- Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage
- Experience with static timing analysis and creation of place and route constraints
- Proficiency in formal verification, linting, and CDC/RDC checking
- Knowledge of asynchronous clock crossings and synthesis implications of RTL
- Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists
- Competence in developing design constraints for synthesis, STA, and P&R hand-off
- Experience with gate-level simulations and understanding the causes and implications of timing violations
- Familiarity with ATPG generation and ATE support (a plus)
- Experience in DFT or physical design (a plus)
Additional Information
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.
About the Company
Renesas is seeking a talented individual for their memory interface products team. These products primarily serve data centers for AI and cloud computing, delivering the highest bandwidth for intensive computing while consuming low power. This exciting role is responsible for the development of the digital sections of leading-edge memory data buffer chips for DDR5, DDR6, and beyond.
Equal opportunity and legal notices
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
From Renesas Electronics's careers page, first listed on Rolev.ai on October 17, 2026. Rolev.ai is not the employer.
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More at Renesas Electronics
All Renesas Electronics jobsCommon questions
Where is the Principal Digital Design Engineer job at Renesas Electronics located?
This Principal Digital Design Engineer position at Renesas Electronics is located in Duluth, GA (On-site). Always check Renesas Electronics's application page for specific state eligibility or relocation policies.
What qualifications are required for Principal Digital Design Engineer at Renesas Electronics?
For the Principal Digital Design Engineer role, Renesas Electronics highlights 12+ years of relevant experience; a bachelor's degree; experience with Verilog RTL, ASIC design methodology, static timing analysis, formal verification, DFT. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Principal Digital Design Engineer position at Renesas Electronics?
This listing links directly to Renesas Electronics's SmartRecruiters application page. You can apply directly on Renesas Electronics's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the SmartRecruiters application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.