Samsung
SemiconductorsDirect Greenhouse career site

Principal Engineer, SOC Design

Pay
$219,000 – $351,000 per year
Location
San Jose, CA · On-site
Job type
Full-time
Level
Executive
Experience
20+ years
Listed
31 days ago

Skills & highlights for this role

  • ASIC design flow
  • SoC synthesis and timing analysis
  • DFT
  • ATE vector generation and silicon bring-up

Also useful

  • UCIe
  • DDR interfaces
  • AMBA bus fabric
  • ARM cores

Stated benefits & perks

  • Medical
  • Dental
  • Vision
  • 401k

Please Note

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World's Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

What You'll Do

  • The DRAM Development Lab (DDL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash.
  • DDL's vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage.
  • The SOC team within DDL focuses on the development of silicon solutions.
  • We are an integral part of Samsung's strong R&D focus & lab innovation engine.
  • We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You'll focus on enhancement of memory and storage capability by developing prototype and production controllers.

Job ID: 43022

Location: Daily onsite presence at our San Jose or Folsom office in alignment with our Flexible Work policy

  • Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
  • Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
  • Reviews 3rd party IPs including ARM cores, DDR controller, and UCIe PHY
  • Responsible for integrating the third part IPs and sub system at top level
  • Work closely with architects and verification engineers to ensure sound design at SoC level.
  • Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

What You Bring

  • Bachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred.
  • Highly motivated with good verbal and written communication skills.
  • Hands on knowledge & experience in ASIC design flow from design to tape out.
  • Experience & Good knowledge in ATE vector generation, testing and silicon bring up.
  • Experience in the commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces.
  • Good understanding of PPA (performance, power, and area) trade-offs.
  • Experience in SoC level synthesis, timing analysis, lint check, CDC checks.
  • Experience in interfacing 3rd party service companies for DFT/PI/PD.
  • Good knowledge and experience in AMBA bus fabric, ARM cores.
  • Self-motivated problem-solver with an ability to work well in a team.
  • You're inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

What We Offer

  • The pay range below is for all roles at this level across all US locations and functions.
  • Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience.
  • We also offer incentive opportunities that reward employees based on individual and company performance.
  • This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
  • In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
  • An investment in your future is an investment in ours.
  • Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
  • Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
  • Care for Family Whatever family means to you, we want to support you along the way-including a stipend for fertility care or adoption, caregiver support, and medical travel support.
  • Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.
  • Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
  • Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.
  • Base Pay Range $219,000—$351,000 USD
Read the original posting

From Samsung's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.

How Rolev.ai helps with this application

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Common questions

What is the salary for the Principal Engineer, SOC Design role at Samsung?

The Principal Engineer, SOC Design posting at Samsung states compensation of $219,000 – $351,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Samsung's official career site.

Where is the Principal Engineer, SOC Design job at Samsung located?

This Principal Engineer, SOC Design position at Samsung is located in San Jose, CA (On-site). Always check Samsung's application page for specific state eligibility or relocation policies.

What qualifications are required for Principal Engineer, SOC Design at Samsung?

For the Principal Engineer, SOC Design role, Samsung highlights 20+ years of relevant experience; experience with ASIC design flow, SoC synthesis and timing analysis, DFT, ATE vector generation and silicon bring-up. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.

How do I apply for the Principal Engineer, SOC Design position at Samsung?

This listing links directly to Samsung's Greenhouse application page. You can apply directly on Samsung's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Greenhouse application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.