Principal Hardware Architect

Overview

As the Principal Memory Controller Architect, you will be part of the team creating the next generation Custom Memory Controller, supporting the latest and upcoming DDR technologies to improve performance of Cobalt CPUs.

You will collaborate closely with product, platform architecture, peer HW, SW, performance architects and execution teams, etc., to ensure our SOCs and IPs enable high performance, efficiency, reliability, and industry-leading systems. This team engages in multiple projects within Microsoft, developing custom silicon for a variety of systems.

We are committed to delivering advanced, custom SoC designs capable of performing complex and high-performance functions in the most efficient way possible

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.

SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.

To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Hardware Architect to join our team!

Responsibilities

• Architecting and development of memory controllers
• Reviewing Memory technology roadmaps including, but not limited to: DDR5, DDR6, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM, MRDIMM, LP-MRDIMM, and emerging memory technologies
• Working closely with memory controller micro-architects, verification and validation to drive features into production
• Working with Vendors evaluate IP and make recommendations
• Work with Performance Modeling team to develop cycle approximate model of the controller and also analyze SOC/platform Azure workload results
• Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy
• Collaborating across teams to come up with the best solution possible with a One Microsoft mindset.
• Challenging the status quo with a growth mindset to push the envelope and enable world-class SOC products across Microsoft.

Required/minimum qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications

• Delivered Architecture, Design or Verification specs for multiple generations of Memory Controllers
• Familiar with DDR, HBM or LPDDR JEDEC specs
• Experience in SoC memory hierarchy/architecture, and knowledge of emerging memory technologies.

Pay and benefits

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.