Principal Network Systems Architect

About the role

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About the Role

As a Principal Network Systems Architect, you will define the scale out, and particularly scale-up network architecture for current and future Cerebras platforms, including proprietary accelerator interconnects, protocols, and switching. Requirements will not arrive as a finished bandwidth and latency specification. Working with application, compiler, runtime, and systems teams, you will study communication patterns, workload partitioning and placement, data and memory movement, synchronization, locality, and failure behavior, then translate them into measurable fabric requirements.

Your primary focus is low-latency scale-up and system fabrics, with enough breadth across scale-out and customer-facing networks to define clean boundaries. You will decide when standards-based or routable technology is right and when a simpler custom protocol or switching design produces a better system result.

Hands-on here means that architectural judgment is grounded in prior low-level implementation, modeling, bring-up, or debugging. You will write specifications, guide models and prototypes, make technical decisions, and stay engaged through implementation and qualification.

Responsibilities

• Set the multi-generation architecture and roadmap for Cerebras scale-up networks and their interfaces to scale-out and customer-facing networks.
• Work with application, compiler, runtime, and communication-library teams to understand mapping and communication choices, then derive the required bandwidth, latency, ordering, availability, and serviceability.
• Define fabric topology, protocols, and switch behavior, including routing, buffering, flow control, reliability, and fault containment. Connect data-plane choices to end-to-end system behavior.
• Decide when to use standards-based technology or merchant silicon and when a custom protocol, switch, link, or offload is justified.
• Use performance models, traffic simulation, prototypes, and lab data to test architecture choices and set acceptance criteria.
• Write architecture and interface specifications, lead design reviews, and drive cross-layer decisions through implementation, bring-up, and qualification.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Typically 12 or more years of relevant industry experience, including principal-level technical ownership of a major networking, switching, accelerator, or HPC system from architecture into implementation or deployment.
• Deep expertise in low-latency or proprietary interconnects, fabric protocols, switch architecture, or a closely related area, with enough data-plane depth to reason about switch pipelines, buffering, routing, flow or congestion control, and reliability.
• Experience deriving network requirements from incomplete workload and system information, with the range to make decisions across software, accelerator I/O, topology, and physical constraints.
• Working knowledge of Ethernet, IP, and RDMA, plus conceptual familiarity with BGP and EVPN and the tradeoffs between routed networks and simpler low-latency scale-up designs.
• Architectural judgment grounded in prior implementation, modeling, silicon, lab, bring-up, or debugging work.
• A record of making clear technical decisions and influencing engineering leaders, implementation teams, suppliers, and customers.

Preferred Experience

Relevant experience may include one or more of the following.

• Proprietary accelerator interconnects or scale-up technologies such as NVLink, xGMI, TPU ICI, Xe Link, or UALink-class systems.
• Switch ASIC, NIC or DPU, accelerator I/O, transport offload, collective acceleration, coherent memory, or custom-fabric work.
• FPGA architecture or mapping experience, or work with other placement-sensitive systems where topology materially affects communication.
• AI or HPC communication stacks such as NCCL, RCCL, MPI, SHMEM, or proprietary collective libraries.
• RoCE, InfiniBand, PCIe, CXL, or other relevant scale-out and I/O technologies.
• Workload-driven modeling, traffic simulation, emulation, or pre-silicon and post-silicon correlation.
• Working awareness of SerDes, packaging, retimers, cabling, optics, and reach constraints.