Principal Silicon Design Verification Engineer
- Location
- Santa Clara | United States, CA · On-site
- Job type
- Full-time
- Level
- Director
- Experience
- 8+ years
- Education
- Bachelor's degree
- Listed
- 29 days ago
Skills & highlights for this role
- UVM
- SystemVerilog
- PCIe
- Verilog
- regression management
Also useful
- NVMe
- RDMA
- Gen6/Gen7 PCIe
About the role
Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP) Develop Test Plan and write unit tests for functional validation Create and Manage regression suites, debug failures, and drive timely resolution Innovate to improve validation efficiency through methodologies and tools Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA Experience with Cluster, SoC, or Fullchip level verification Prior verification experience with PCIe, both at the Transaction and Data Link Layer Strong proficiency in Verilog, System Verilog, and UVM based testbench environment.
Good understanding of computer architecture and digital design fundamentals Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to succesfull tapeout.
From Microsoft's careers page, first listed on Rolev.ai on October 11, 2026. Rolev.ai is not the employer.
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Common questions
Where is the Principal Silicon Design Verification Engineer job at Microsoft located?
This Principal Silicon Design Verification Engineer position at Microsoft is located in Santa Clara | United States, CA (On-site). Always check Microsoft's application page for specific state eligibility or relocation policies.
What qualifications are required for Principal Silicon Design Verification Engineer at Microsoft?
For the Principal Silicon Design Verification Engineer role, Microsoft highlights 8+ years of relevant experience; a bachelor's degree; experience with UVM, SystemVerilog, PCIe, Verilog, regression management. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Principal Silicon Design Verification Engineer position at Microsoft?
This listing links directly to Microsoft's application page. You can apply directly on Microsoft's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.