Principal Silicon Engineer
- Pay
- $142,800 – $274,800 per year
- Location
- Mountain View | United States, CA · On-site
- Job type
- Full-time
- Level
- Lead / Staff
- Experience
- 8+ years
- Education
- Bachelor's degree
- Listed
- 28 days ago
Skills & highlights for this role
- US citizenship verification
- export control eligibility
- RTL design
- CDC/RDC/VCLP/LINT checks
- silicon design
About the role
Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, and high-quality hardware implementations Lead the capture and validation of design intent for digital and mixed‑signal blocks, ensuring accurate constraints and seamless integration across front‑end and physical design flows.
Provide static timing leadership for mixed‑signal interfaces, driving timing closure, exception quality, and correlation across MMMC corners. Partner closely with RTL, PD, mixed‑signal, DFT, and CAD teams to resolve cross‑domain issues and maintain alignment on timing, power, and functional requirements.
Contribute to design automation including leveraging AI, constraint‑checking, and flow improvements that enhance execution efficiency and PPA. Operate with limited direction, demonstrating strong ownership, attention to detail, and the ability to communicate clear, data‑driven status, risks, and mitigation plans to program leadership.
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.
To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status.
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
1+ year(s) experience working on or leading projects from beginning-to-end.
8+ years of experience in RTL design and design checks (CDC/RDC/VCLP/LINT) 8+ years of experience in Synthesis, Timing constraints and Power Performance Area (PPA) trade-offs Proficiency in RTL to Physical Design collateral development including timing and synthesis constraints Knowledge of full RTL2GDS flow Hands‑on experience with industry tools for synthesis, STA, and PD flows (e.g., PrimeTime, Genus/DC, Innovus/ICC2) Proficiency in recent synthesis tool capabilities and methods for QoR improvement Proficiency in static timing analysis Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification Proficiency in translating physical design results into feedback for flow or RTL improvement Proficiency in Tcl, Python
Equal opportunity and legal notices
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C.
From Microsoft's careers page, first listed on Rolev.ai on October 11, 2026. Rolev.ai is not the employer.
How Rolev.ai helps with this application
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Common questions
What is the salary for the Principal Silicon Engineer role at Microsoft?
The Principal Silicon Engineer posting at Microsoft states compensation of $142,800 – $274,800 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Microsoft's official career site.
Where is the Principal Silicon Engineer job at Microsoft located?
This Principal Silicon Engineer position at Microsoft is located in Mountain View | United States, CA (On-site). Always check Microsoft's application page for specific state eligibility or relocation policies.
What qualifications are required for Principal Silicon Engineer at Microsoft?
For the Principal Silicon Engineer role, Microsoft highlights 8+ years of relevant experience; a bachelor's degree; experience with RTL design, CDC/RDC/VCLP/LINT checks, silicon design. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Principal Silicon Engineer position at Microsoft?
This listing links directly to Microsoft's application page. You can apply directly on Microsoft's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.