Research Scientist / Engineer - Performance Optimization

About the role

You'll make Luma's multimodal models fast - profiling and optimizing GPU, CPU, and accelerator code so they train efficiently and deploy at scale without sacrificing quality. You'll write the kernels and operations that get the most out of the hardware.

This is deep performance work: fused kernels, tensor cores, Triton and CUDA, distributed multi-node deployment. It fits someone with expert GPU-optimization skills and a deep understanding of transformer internals. If you're not at home in CUDA, Triton, and profilers, this is the wrong depth.

What You'll Own

• Profile and optimize GPU/CPU/accelerator code for maximum utilization and minimal latency.
• Write high-performance PyTorch, Triton, and CUDA, dropping to custom operations when needed.
• Develop fused kernels and leverage tensor cores and modern hardware features across platforms.
• Optimize model architectures and implementations for distributed multi-node production deployment.
• Build performance monitoring and analysis tools and automation.
• Research and implement cutting-edge optimization techniques for transformer models.

First 90 Days

One way the first 90 could unfold.

• Days 1-30 - Immerse & Diagnose: Profile the current training and inference paths and find the biggest performance wins.
• Days 30-60 - Ship & Validate: Land a kernel or architecture optimization that measurably improves utilization or latency.
• Days 60-90 - Scale & Systemize: Build the monitoring and automation that keeps performance gains from regressing.

What You Bring

• Expert-level Triton/CUDA programming and GPU optimization.
• Strong PyTorch skills, including kernel development and custom operations.
• Proficiency with profiling tools (NVIDIA Nsight, torch profiler, custom tooling).
• Deep understanding of transformer architectures and attention mechanisms.

Nice to Have

• Experience with compilers and exporters (torch.compile, TensorRT, ONNX, XLA).
• Experience optimizing inference workloads for latency and throughput.
• Triton compiler and kernel fusion techniques.
• Knowledge of warp-level intrinsics and advanced CUDA optimization.