RTL Design Lead/IC Front-End Architect/Datapath Lead

About the Role

You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify - this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.

About the role. You define the digital front-end micro-architecture - the spec the design team implements - and personally own the high-speed datapath that moves data between UCIe and the optical front end. This is the architectural center of the chip: the datapath, the UCIe streaming interface, in-house IP, and the interface to the optical engine all converge in your blocks. As a founding hire you set the partitioning, interfaces, and coding/CDC standards the whole front end follows.

What you'll own

• Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to.
• Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team.
• The high-speed datapath: per-lane alignment/deskew/mux, the UCIe streaming /RDI adapter, elastic FIFOs, and custom logic.
• Transport/link framing/mapping and the adaptation logic.
• Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps (with the backend team).
• Clocking, reset, and low-power architecture - clock/reset domains, gating strategy, and UPF power intent.
• Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA) coverage that designers own before handoff to DV.
• Architectural DFT and debug provisioning - scan-friendly structure and on-die observability/controllability for a die you can't probe (with the DFT and DV leads).
• IP integration and interface/register conventions; parameterization for configurability across lane counts/configurations.
• Architectural trade-offs with the modelling lead (latency, buffering, datapath sampling/observability) and the DV lead (verifiability and debug).
• Lead, grow, and mentor the front-end design team as the group scales (datapath, interfaces, integration).

Required

• 10+ years digital design / micro-architecture, with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.
• Experience designing the datapath of a network switch/NIC card or memory controller at a major XPU / fabric vendor (or a comparable high-throughput, high-reliability datapath).
• Solid understanding of scale-up vs. scale-out interconnect architectures and their bandwidth/latency trade-offs.
• Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline.
• Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew.
• Proven ownership of front-end design methodology - lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test and physical-closure collaboration.
• Track record translating system requirements into an implementable, verifiable architecture spec.

Preferred

• UCIe (or PCIe/CXL/CHI) interface architecture; die-to-die / chiplet experience.
• FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
• Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.

What We Offer

• Competitive salary commensurate with experience
• Comprehensive benefits package including health, dental, and vision
• Professional development opportunities and certification support
• Access to cutting-edge technology and cloud platforms
• Collaborative work environment with cross-functional teams