Senior Debug Verification Engineer
- Pay
- $149,100 – $215,000 per year
- Location
- San Jose, CA · On-site
- Job type
- Full-time
- Level
- Senior
- Experience
- 8+ years
- Listed
- 30 days ago
Skills & highlights for this role
- SystemVerilog
- UVM verification methodology
- formal verification
- Linux/Unix scripting
- Perl
- Python
Also useful
- JTAG
- PCIe
- FPGA emulation
- UltraSoC/Tessent Embedded Analytics
About the Role
As a Sr. Debug Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan. Using system full application to verify performance and identify short falls.
Key Responsibilities
- Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification.
- Create testcase and testbench with UVM methodology
- Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification
- Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.
- Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
- Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.
- Coordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan
- Experience on Emulation will be an add on.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$149,100 - $215,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#MD-1
Qualifications
Minimum Qualifications - 8+ years of experience with complex ASIC designs and/or verification - 8+ years of experience with SystemVerilog language - 8+ years of experience on UVM verification methodology, and formal verification method - 8+ years of experience scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.
- Strong communication skills and the ability to work with a team spread across different geography sites
- Job Type: Regular
- Shift: Shift 1 (United States of America)
- Primary Location: San Jose, California, United States
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
Equal opportunity and legal notices
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
From Altera's careers page, first listed on Rolev.ai on October 10, 2026. Rolev.ai is not the employer.
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Common questions
What is the salary for the Senior Debug Verification Engineer role at Altera?
The Senior Debug Verification Engineer posting at Altera states compensation of $149,100 – $215,000 per year. It is listed as a full-time position. Final pay may depend on location, experience, and interview evaluation on Altera's official career site.
Where is the Senior Debug Verification Engineer job at Altera located?
This Senior Debug Verification Engineer position at Altera is located in San Jose, CA (On-site). Always check Altera's application page for specific state eligibility or relocation policies.
What qualifications are required for Senior Debug Verification Engineer at Altera?
For the Senior Debug Verification Engineer role, Altera highlights 8+ years of relevant experience; experience with SystemVerilog, UVM verification methodology, formal verification, Linux/Unix scripting, Perl, Python. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Senior Debug Verification Engineer position at Altera?
This listing links directly to Altera's Workday application page. You can apply directly on Altera's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the Workday application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.