Senior Security IP Engineer

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.

SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance.

To achieve this goal, the SCIPS (Shared and Custom IP & Silicon) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Security IP Design Engineer to join the team.

#SCHIE #CSME

Responsibilities

The candidate for this position will be expected and able to complete the following responsibilities:

• Own end-to-end development of security IPs from architecture and microarchitecture definition through silicon validation.
• Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality IP solutions.
• Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.
• Lead design signoff activities including CDC, RDC, LINT, synthesis, STA, and timing closure.
• Implement and integrate hardware security technologies such as cryptographic accelerators, root-of-trust, secure boot, and key management.
• Drive pre-silicon and post-silicon debug, silicon bring-up, and root-cause analysis of complex system issues.
• Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.

Required Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Screening Requirements

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable

Preferred Qualifications

• 8+ years of hardware design experience
• Expertise in Digital Design including microarchitecture specification development and RTL coding
• Expertise in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and LINT closure
• Experience in developing/optimizing high speed CMOS designs and evaluating PPA tradeoffs Proficiency in Verilog, System Verilog, and scripting languages such as Python or Perl
• Design knowledge of the industry standard bus interfaces such as AMBA AXI protocol
• Experience in basic floor planning, static timing analysis/closure and engaging with physical design teams
• Experience with driving chip design quality through design and checklist reviews
• Good communication and a self-motivated individual that can collaborate across teams within Microsoft
• Worked in leading-edge technologies: 5 nm or newer
• Experience working with Cryptography Standards e.g., AES, SHA, Elliptic Curve Cryptography is a plus.

Pay and benefits

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.