Silicon Packaging Engineer
- Location
- Sunnyvale, CA · On-site
- Job type
- Full-time
- Level
- Lead / Staff
- Experience
- 8+ years
- Education
- Master's degree
- Listed
- 13 days ago
Skills & highlights for this role
- Semiconductor packaging
- Flip chip packaging
- 2.5D packaging
- 3D packaging
- Advanced packaging development and assembly process
- Concept-to-production product development
- Vendor qualification
- Technical communication
Also useful
- AI/ML hardware experience
- AI/HPC hardware development
- Machine learning cluster integration
- Design of Experiments (DOE)
- Open Compute Project familiarity
- Heterogeneous integration
- ODM/OSAT partner management
About the role
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- Silicon Packaging Engineer
- Silicon Packaging Engineer
- Sunnyvale, CA +1 location
- Engineering
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Meta is looking for an experienced Silicon Packaging Engineer for its Ecosystem and Technical Operation team. The ideal candidate will be able to prioritize competing workstreams across a cross-functional engineering environment based on impact, deadlines, and stakeholder needs. They will have experience with hardware development and integration of machine learning clusters, both server and fabric. They will be very familiar with AI/HPC hardware development, and will be data-driven and focused on the impact they can create as part of a engineering team.
The Meta Infrastructure team designs, builds, brings-up, tests and integrates hardware systems that power Meta’s platforms, deployed in data centers worldwide, from silicon to sheet metal. Designs are published through the Open Compute Project Foundation. This is an opportunity to join our team and help us build some of the world’s most open and efficient machine learning platforms.
We are building a competency in packaging design and technology to support the development of custom silicons for Infrastructure hardware as well as to develop packaging solutions that are optimal for our AI/ML products and system level performance.
Silicon Packaging Engineer Responsibilities
- Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging, design feasibility studies and analyses to ensure good manufacturing at ODM
- Lead development of next-generation advanced packaging technologies from concept to product, including test vehicle definition and building with ecosystem partners
- Work with internal Si, architecture and system teams, and externally with engaged partners, ODM, design houses and OSAT companies
- Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package form factor for next-generation versions of current products
- Influence ASIC vendors, foundry, ODM and OSAT partners' roadmaps and align with Meta ASIC roadmaps for the development of advanced packaging technologies (SMT, solder ball attach, and other assembly process)
- Participate early in Si/package/PCB/system co-design and ODM SMT manufacturing work in product development design reviews, providing feedback on manufacturability and helping incorporate the latest technology advancements and design rules
- Create, conduct and analyze Design of Experiments (DOE) for development and sustaining activities
- Work cross-functionally with design, NPI, quality and reliability, and manufacturing teams, and support new technology integration into products
Support selection and qualification of external partners
- Collaborate with internal and external stakeholders to ensure seamless integration of packaging technology into product development cycles
- Stay abreast of the latest advancements in advanced packaging technologies and market trends
- Identify and evaluate emerging technologies with potential for future applications
- Ability to travel internationally, typically once per quarter
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience
- 8+ years of experience in semiconductor packaging with direct ownership of advanced packaging development and assembly process and manufacturing
- In-depth knowledge of flip chip, 2.5D and 3D packaging technologies
- Experience taking products from concept to production, including development of manufacturing specifications, vendor qualifications, and improvement of manufacturing efficiencies and costs
- Experience communicating technical packaging decisions in writing and in reviews to cross-functional engineering and manufacturing stakeholders
- Experience working effectively with cross-functional teams
- Willingness to travel internationally, typically once per quarter
Preferred Qualifications
- Experience working with ODM, assembly packaging, OSAT, and foundry partners
- Knowledge of packaging and assembly industry standards
- Proven understanding of fanout advanced packaging technologies
- Hands-on experience in interposer or fanout package design for both organic and inorganic interposer with or without bridges such as CoWoS-L, CoWoS-R, EMIB, embedded fanout bridge from OSAT
- Proven technical understanding of the full range of semiconductor packaging design, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques
- In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps and advanced packages interaction with board-assembly constraints
- Master's degree or PhD in Materials Science, Mechanical Engineering, or a related discipline
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United States of America: $146,000/year to $209,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.
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From Meta's careers page, first listed on Rolev.ai on October 27, 2026. Rolev.ai is not the employer.
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Common questions
Where is the Silicon Packaging Engineer job at Meta located?
This Silicon Packaging Engineer position at Meta is located in Sunnyvale, CA (On-site). Always check Meta's application page for specific state eligibility or relocation policies.
What qualifications are required for Silicon Packaging Engineer at Meta?
For the Silicon Packaging Engineer role, Meta highlights 8+ years of relevant experience; a master's degree; experience with Semiconductor packaging, Flip chip packaging, 2.5D packaging, 3D packaging, Advanced packaging development and assembly process, Concept-to-production product development. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the Silicon Packaging Engineer position at Meta?
This listing links directly to Meta's application page. You can apply directly on Meta's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.