Apple
SemiconductorsDirect employer career site

SoC Physical Design Engineer, PnR

Location
San Diego, CA · On-site
Job type
Full-time
Level
Mid-level
Listed
29 days ago

Skills & highlights for this role

  • physical design
  • place and route
  • static timing analysis

Also useful

  • Verilog
  • VHDL
  • Python
  • TCL

Summary

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products.

The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

About the role

In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs Knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor-planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include:

  • Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
  • Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
  • Timing, physical and electrical verification, and driving the signoff closure for the partitions.
  • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

  • Minimum BS with 0+ years experience.
  • Basic understanding of logic gates.

Preferred Qualifications

  • Previous internship/co-op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
  • Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields.
  • Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE.
Read the original posting

From Apple's careers page, first listed on Rolev.ai on October 12, 2026. Rolev.ai is not the employer.

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Common questions

Where is the SoC Physical Design Engineer, PnR job at Apple located?

This SoC Physical Design Engineer, PnR position at Apple is located in San Diego, CA (On-site). Always check Apple's application page for specific state eligibility or relocation policies.

What qualifications are required for SoC Physical Design Engineer, PnR at Apple?

For the SoC Physical Design Engineer, PnR role, Apple highlights experience with physical design, place and route, static timing analysis. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.

How do I apply for the SoC Physical Design Engineer, PnR position at Apple?

This listing links directly to Apple's application page. You can apply directly on Apple's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.