SoC Power Flow Methodology Engineer
- Location
- Cupertino · On-site
- Job type
- Full-time
- Level
- Senior
- Education
- Bachelor's degree
- Listed
- 14 days ago
Skills & highlights for this role
- VLSI design
- SoC design process
- Python
- Perl
- TCL
- Scripting
Also useful
- Low-power design techniques
- AI/ML
- Power analysis
- Power optimization
- Power verification
- RTL development and verification
- Logic synthesis
- Place-and-route (P&R)
Summary
Are you passionate about crafting solutions to intricate challenges? Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips!
Responsible for developing and improving low-power flow algorithms using AI and machine learning, which significantly impacts the work of many designers involved in mobile system-on- chips
About the role
In this role, you’ll develop innovative automated tools and capabilities for the Silicon
Engineering Power team. Your contributions will enable the creation of chips with unprecedented power efficiency. You’ll be involved in the architecture, implementation, and validation of advanced low-power design and verification workflows. Additionally, you’ll shape low-power strategies for emerging technologies.
Your responsibilities will encompass the development of flows and tools for power analysis, optimization, and verification, seamlessly integrated into stages such as RTL development/ verification, synthesis, or place-and-route (P&R). You’ll actively leverage various AI tools to innovate new solutions and enhance existing ones. Additionally, you’ll collaborate with design teams to address queries, resolve issues, and ensure the smooth adoption of these methodologies.
Minimum Qualifications
Bachelors Degree in a relevant field
Preferred Qualifications
- Solid grasp of VLSI designs and SOC design processes.
- Enthusiasm for scripting and leveraging low-power expertise to innovate software solutions.
- Enthusiasm for leveraging AI/ML to innovate low-power methodologies and flows.
- Experience in flow development and algorithm design using Python/Perl/TCL.
- Demonstrated proficiency in contemporary software testing and development methodologies.
- Familiarity with low-power principles (e.g., low-power design techniques) is advantageous.
From Apple's careers page, first listed on Rolev.ai on October 27, 2026. Rolev.ai is not the employer.
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Common questions
Where is the SoC Power Flow Methodology Engineer job at Apple located?
This SoC Power Flow Methodology Engineer position at Apple is located in Cupertino (On-site). Always check Apple's application page for specific state eligibility or relocation policies.
What qualifications are required for SoC Power Flow Methodology Engineer at Apple?
For the SoC Power Flow Methodology Engineer role, Apple highlights a bachelor's degree; experience with VLSI design, SoC design process, Python, Perl, TCL, Scripting. Rolev.ai can score your existing resume against these requirements and show any skill gaps before you apply.
How do I apply for the SoC Power Flow Methodology Engineer position at Apple?
This listing links directly to Apple's application page. You can apply directly on Apple's site, or use Rolev.ai to check your resume fit, generate a zero-hallucination tailored resume and cover letter for this posting, and autofill the application form in 1 click with the Rolev.ai Chrome extension. You always review the form and press Submit yourself.