Software Engineer, AI Kernels & Performance Optimization — MTIA Software

About the role

Meta designs and deploys its own AI systems.

The MTIA Software team is part of the AI & Compute Foundation (ACF) organization within Meta Infrastructure. Because the hardware is ours, the software is ours too: we build the entire stack a chip vendor would normally supply — compiler and LLVM toolchain, runtime, kernel authoring frameworks and libraries, developer tooling, and deep PyTorch integration — and we co-design it with the silicon teams generation over generation.

Within that stack, the AI kernel and optimization software development team drives the layer where architecture meets arithmetic. Our mission is performance *and* programmability at scale: hit roofline enablements on the workloads that matter, and make kernel authoring accessible enough that the whole organization can close coverage gaps without funneling every problem through a handful of experts.

We do this by shipping high-performance kernel libraries with broad PyTorch operator coverage, by building the C++ and Python kernel authoring frameworks and DSL surfaces that others build on, and by writing production kernels against new architectures long before first silicon — turning hardware proposals into measured roofline evidence while the design can still change.

We are hiring an experienced kernel and performance engineer to take on this role at a senior level. You will own the performance of workloads that serve billions of people, from the innermost loop of a fused attention kernel to the numeric decisions that determine whether a model converges. You will read hardware specifications and RTL-adjacent documentation as easily as you read code, and you will be expected to say clearly when the hardware — not the software — is the problem. Your findings will change what gets built next.

This is a hands-on engineering role with wide latitude. The problems aren't incremental.

What you'll work on

• Roofline-level kernels. GEMM and attention variants, normalization, collectives, elementwise and reduction fusions, sparse and quantized paths — implemented against novel architectural features (matrix engines, on-chip reduction fabrics, software-managed memory hierarchies) and tuned until the remaining gap to the machine's limit is explainable in a sentence.
• Numerics under precision constraints. Low-precision formats (FP8, MX-style block-scaled types, integer quantization) where the difference between a correct scale choice and a plausible one is several decibels of signal, and where the fix has to work on silicon that has already been taped out.
• Kernel authoring frameworks. Templateized, composable C++ kernel SDKs in the spirit of CUTLASS, Python DSLs in the spirit of Triton and CuTe, and the compiler-facing interfaces that let automated codegen reach performance that used to require a specialist.
• Pre-silicon and bring-up. Kernels on simulators and emulators, validating architectural features and rooflines before tapeout, then first-light bring-up on real parts.
• Software mitigations for hardware realities. Every chip ships with something you wish were different. Finding the workaround that recovers most of the lost performance — and generalizing it so nobody rediscovers it — is core to the job.