Sr. ASIC RTL Design Engineer, SI Hardware

About the role

• Sr. ASIC RTL Design Engineer, SI Hardware | Tesla (Tesla SI)
• Location: Austin, Texas | Req ID: 283671 | Job Type: Full-time
• What to Expect

The Tesla SI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced SI inference chips tailored to accelerate Tesla’s machine learning capabilities.

A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's SI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance.

By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

The Tesla SI Hardware team is looking for an ASIC RTL Design Engineer to work on industry leading SI accelerators in Palo Alto, CA and Austin, TX. Candidate is expected to implement and document microarchitecture specifications, define system-level functional requirements, and deliver high quality design to achieve project targets. Open to level based on experience and panel feedback.

What You'll Do

• Micro-architecture specification and design
• Deliver Performance, Area and Power-efficient RTL design
• Specification, microarchitecture, and RTL design of accelerators, memory and network subsystems
• Work with the architecture and software teams to achieve design targets
• Balance performance, power, safety, and cost requirements
• Trade-off functional, physical and performance requirements
• Work with cross-functional teams, including implementation, verification, and performance engineers
• Design for synthesis

What You'll Bring

• High performance (low latency, high bandwidth) design techniques
• Area and power-efficient complex RTL design
• Low power microarchitecture techniques
• Verilog RTL logic design
• Experience with simulators and waveform debug tools
• Knowledge of logic design principles, including timing and power implications
• Degree in Electrical Engineering, Computer Science, or equivalent experience
• 5 or more years of industry experience
• Experience with IEEE floating point is a plus
• Experience with RTL design across specialties such as SoC, CPU, and GPU