Sr. Physical Design Engineer

Role Overview

We are seeking a Senior Physical Design Engineer to join our silicon design team developing high-performance ASIC using TSMC advance process nodes, including 5nm and 3nm. In this role, you will own physical implementation from RTL to GDSII, drive timing and power closure for ultra-high-speed designs, and work closely with RTL, STA, IP, and verification teams to solve complex implementation challenges unique to advanced-node and high-speed transceiver architectures.

Key Responsibilities

• Physical Implementation: Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes.
• Timing, Power, and Area Closure: Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip.
• Advanced Physical Design: Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing.
• Signoff and Tape out: Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard verification tools.

Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• Experience: 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below.
• Physical Design Expertise: Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging.
• Tools and Automation: Hands-on experience with tools such as Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Simens Calibre etc, along with strong scripting skills in Tcl, Python, or Perl.

Preferred Qualifications (Bonus)

• High-Speed PHY Implementation: Experience with high-speed PHY such as SerDes, UCIe etc physical design implementation.
• Advanced-Node Signoff: Familiarity with EM/IR analysis, power grid optimization, congestion analysis, physical verification, and tapeout signoff in advanced semiconductor process nodes.
• High-Frequency Design Exposure: Experience supporting high-frequency datapath or DSP-heavy designs is a plus.
• 2.5D or 3D design experience: Experience with TSMC CoWoS or SoIC-X design experience is a strong plus.

What we offer

• Competitive salary commensurate with experience
• Comprehensive benefits package including health insurance
• Professional development opportunities and certification support
• Access to cutting-edge technology and cloud platforms
• Collaborative work environment with cross-functional teams