Sr. Physical Design Flow & Methodology Engineer

Responsibilities

• Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL.
• Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction.
• Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the successful ones into production flows.
• Build tools for regression testing, QoR tracking and dashboards so flow changes are measurable and safe.
• Support the implementation teams by debugging flow problems, reproducing tool issues and working with EDA vendors on fixes.
• Run blocks through the flow as needed to validate methodology changes, including timing closure, ECOs and DRC/LVS cleanup.
• Write clear documentation and train the PD team on new flows and tools.

Qualifications

• Bachelor's in Electrical Engineering, Computer Engineering or Computer Science, plus at least 5 years of related industry experience.
• Has contributed to at least one ASIC or mixed-signal chip through tapeout.
• Solid understanding of the RTL-to-GDS flow, including synthesis, place-and-route, clock tree synthesis, static timing analysis and physical verification.
• Strong Python skills (maintainable, tested, version-controlled code) and working knowledge of TCL and shell scripting.
• Practical experience using AI coding assistants or LLM-based tools to automate engineering work, or a strong interest in learning to.
• Strong teamwork skills, with the ability to work with PD, RTL, verification, CAD and photonics teams.
• Comfortable with ambiguity and changing priorities in a fast-paced research-driven environment.

Preferred Qualifications

• Master's degree with at least 3 years of experience in physical design OR PhD in Electrical Engineering, Computer Engineering or Computer Science
• Hands-on experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Pegasus) and/or Siemens Calibre.
• Experience developing or owning a production PD flow, or contributing to CAD and methodology infrastructure.
• Familiarity with advanced process nodes (FinFET or newer).
• Experience with software engineering practices: Git, CI/CD, unit and regression testing, code review.
• Experience with LLM APIs, agent frameworks or ML techniques applied to EDA problems.
• Experience with layout data formats and tools (GDS/OASIS, LEF/DEF, KLayout scripting).
• Interest in silicon photonics and in custom or photonic layout automation.

Pay and benefits

We offer competitive compensation. The base salary range for this role determined based on location, experience, educational background, and market data.

Salary Range

total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution.

$154,000 - $175,000 USD

Benefits

• Comprehensive Health Care Plan (Medical, Dental & Vision)
• Retirement Savings Matching Program
• Life Insurance (Basic, Voluntary & AD&D)
• Generous Time Off (Vacation, Sick & Public Holidays)
• Paid Family Leave
• Short Term & Long Term Disability
• Training & Development
• Commuter Benefits
• Flexible, hybrid workplace model
• Equity grants (applicable to full-time employees)

Export Control

Candidates should have capacity to comply with the federally mandated requirements of U.S. export control laws.