Sr. Staff Device Engineer, Memory, Terafab

About the role

• Sr. Staff Device Engineer, Memory, Terafab | Tesla (Terafab)
• Location: Austin, Texas | Req ID: 285125 | Job Type: Full-time
• What to Expect

Tesla is seeking a Staff Device Engineer in Austin to define memory device technology from the design side. This role owns memory cell and periphery device design, design-technology co-optimization (DTCO), and the models and design rules that let memory design use the technology.

DRAM is the core of the work, with embedded SRAM in the same scope. You will build design enablement, from TCAD and SPICE models through the process design kit (PDK) and device design rules, and set the memory device roadmap with the design team.

What You'll Do

• Own memory device design for DRAM and embedded SRAM, including the cell transistor, bitcell, array, and periphery devices
• Define device targets for speed, power, retention, sensing margin, and variability through design-technology co-optimization (DTCO)
• Build and govern the PDK and device design rules that support memory technology definition and design enablement
• Run TCAD process and device simulation to explore cell and periphery options and set electrical targets before silicon
• Develop device models and correlate them to silicon, including compact models used in SPICE simulation of array and periphery circuits
• Partner with memory design to enable design closure, from sensing margin and design-rule intent through corner behavior
• Use parametric, array, and product electrical data to close gaps between TCAD, SPICE, and silicon
• Set the memory device and modeling roadmap, and lead technical decisions with design and technology development
• Mentor device and design-enablement engineers and set the methods for modeling, design rules, and technology decisions

What You'll Bring

• 10+ years in memory device engineering, with the core of that work in device design, TCAD, or design enablement
• Degree in Electrical Engineering, Physics, Materials Science, or a related field, or equivalent experience
• Direct experience designing DRAM or embedded SRAM devices, including bitcell, array transistor, and periphery behavior
• Demonstrated DTCO work that turned memory device physics into design rules, models, and product targets
• Experience building or owning PDK content and device design rule governance
• Proficiency in TCAD process and device simulation and in SPICE or compact device modeling
• Record of correlating simulation to silicon using parametric and array data, design of experiments, and statistical analysis
• Strong foundation in semiconductor physics, transistor operation, scaling limits, variability, and device characterization
• Proven ability to lead technical direction with design teams without direct authority, and to mentor other engineers
• Clear communication of device, model, and design-rule decisions to design, technology, and leadership audiences