STA & Custom Logic Design Engineer

Summary

Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The Analog/Mixed Signal Design team is searching for a self-motivating engineer for the role of Custom Logic Design and STA engineer.

As a member of the team, we will be working on the leading-edge technology to build best-in-class custom mixed-signal designs used to connect our world-class products to the world as well as optimizing their performance. You will become part of a development team that cultivates engineering excellence, creativity, and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in this type of environment. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products?

About the role

In this role, you will perform timing analysis on custom design circuits, delivery timing views to integration teams, as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers, and cross-functional teams at the silicon and module levels.

Responsibilities

• Custom design timing closure ownership throughout the entire project cycle.
• Develop and implement STA constraints from specs.
• Perform block- and chip-level static timing and noise analysis.
• Design and characterize transistor- and gate-level custom digital circuits in mixed-signal chips.
• Work with RTL and custom design teams on timing changes and propose correct-by-construction designs and methodologies.
• Assist design verification and DFT team to debug functional and testing issues.
• Assist CAD in developing and maintaining methodologies and flows related to timing verification and closure.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience.
• Solid understanding of timing analysis concepts such as setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, rise/fall time balancing, etc.
• Experience of timing analysis and verification in high-speed design such as SerDes and ADC.
• In-depth knowledge and analytical understanding of mixed-signal design techniques.
• Strong track record of delivering silicon IPs with design and verification.
• Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.

Preferred Qualifications

• Master’s Degree with 8+ years of relevant industry experience.
• Experience with STA tools such as NanoTime, PrimeTime, or Tempus.
• Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.
• Experience in SRAM design.
• Experience in timing / SDC constraints generation and management.
• Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with POCV.
• Proficiency in scripting languages (Python, Tcl or Perl).