Staff Engineer, Digital ASIC Design - Storage Controllers

About the Role

Join our digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. This role offers opportunities across the controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. You will translate product requirements into microarchitecture specifications, implement high-quality RTL, and collaborate with verification and physical design teams to deliver production-ready silicon.

You will help shape the performance, power efficiency, and scalability of future storage products, with potential opportunities to explore computational storage, storage for AI workloads, next generation SSD architectures as our technology and product roadmap evolve.

Responsibilities

• Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
• Develop clear microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
• Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
• Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
• Collaborate with design verification engineers to develop verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
• Work with physical design and timing teams on timing constraints, critical-path optimization, and timing closure.
• Lead design reviews, provide technical guidance to other engineers, and coordinate with cross-functional teams to meet project milestones.

Minimum Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, or a closely related field.
• Demonstrated experience independently owning complex digital ASIC blocks, with technical depth and judgment appropriate for a Staff Engineer.
• Strong proficiency in synthesizable Verilog or SystemVerilog and synchronous digital design fundamentals.
• Working knowledge of ASIC development flows, including simulation using VCS or an equivalent tool, lint, CDC analysis, logic synthesis, and static timing analysis and timing closure.
• Ability to write clear microarchitecture specifications, debug complex design issues, and communicate effectively across design, verification, and physical design teams.

Preferred Qualifications

• Experience designing PCIe or NVMe controller logic.
• Experience with SSD controller architectures, NAND interfaces, or flash storage systems.
• Familiarity with AXI protocols, on-chip interconnects, and high-throughput data movement.
• Experience with CPU subsystems or UCIe interfaces.
• Experience delivering ASIC designs through tapeout and supporting silicon bring-up, validation, or production debug.

Regarding Compensation

SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.

The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.

Benefits

• Top Tier health insurance
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees