Apple Jobs - Page 52
Open positions at Apple, newest first. Each listing links to the company's own application page.
- Open positions
- 1,491
Newest Apple openings
San Diego, CA (On-site) · 29 days ago
Join the Wireless Technologies and Ecosystems organization and be part of an outstanding team of engineers driving innovation and developing products used by millions worldwide.
- Full-time
- Mid-level
- 2+ years
- Bluetooth protocol stack
- C
- C++
Module Process Engineer
On-siteSan Francisco, CA (On-site) · 29 days ago
Apple is looking for a Module Process Engineer to join Display Module Technology team!
- Full-time
- Senior
- 10+ years
- process FMEA
- DOE
- statistical process control
Fullerton, CA (On-site) · 29 days ago
Imagine what you could do here.
- Full-time
- Mid-level
- 1+ years
- customer experience
- product demonstration
- direct sales
Audio Engineer
On-siteAustin, TX (On-site) · 29 days ago
In Places, we don’t sit back and let things happen, we make things happen, and we do this in service to all Apple employees and customers.
- Full-time
- Senior
- 7+ years
- console bussing and routing
- Dante
- AVB
Manufacturing Quality Engineer
$134k – $202k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- design of experiments
- failure analysis
- statistical analysis (JMP)
Prototyping Engineer
On-siteCupertino, CA (On-site) · 29 days ago
We are seeking a visionary Prototyping Engineer who operates at the bleeding edge of spatial computing, generative AI, and computational photography.
- Full-time
- Lead / Staff
- 3+ years
- real-time computer graphics
- novel view synthesis
- optical physics
Austin, TX (On-site) · 29 days ago
At Apple, our greatest resource is our people.
- Full-time
- Senior
- 7+ years
- Snowflake
- SQL
- Python
FE Engineer
On-siteAustin, TX (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- Verilog
- RTL design
- static timing analysis
FE Engineering
On-siteAustin, TX (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 1+ years
- logic synthesis
- static timing analysis
- Verilog
System Product Design Engineer
$174k – $225k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 2+ years
- injection molding
- CAD design tools
- design of experiments
Digital Circuit Design Engineer
Direct ATSAustin, TX · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- SystemVerilog
- UVM
- RTL verification
GPU Physical Design Engineer
On-siteAustin, TX (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Senior
- 3+ years
- Cadence Innovus
- place and route
- TCL
FE Engineering
$174k – $225k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 1+ years
- Verilog
- SystemVerilog
- SystemC
Physical Design Engineer
On-siteAustin, TX (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 3+ years
- Innovus
- Primetime
- static timing analysis
Product Quality
$145k – $202k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 1+ years
- pFMEA
- Design of Experiments (DOE)
- root cause analysis
Design Verification Engineer
$142k – $214k/yrSan Diego, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Senior
- Verilog/SystemVerilog
- UVM
- Palladium
Design Verification Engineer
$174k – $225k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- SystemVerilog
- UVM
- RTL design
Silicon Product Engineer
$150k – $218k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- statistical analysis
- JMP
- Python
Module Design Engineer
$150k – $225k/yrCupertino, CA (On-site) · 29 days ago
Imagine what you can do here.
- Full-time
- Mid-level
- 3+ years
- schematic capture
- PCB layout
- Allegro
CPU Implementation Engineer
On-siteAustin, TX (On-site) · 29 days ago
Imagine what you can do here.
- Part-time
- Mid-level
- 2+ years
- RTL-to-GDS flow
- static timing analysis
- place-and-route
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