Design Verification Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

About the role

APPLE INC has the following available in San Diego, California. Bring up the emulation platform for large Wireless Socs along with their mixed signal components. Develop monitors and checkers for Emulation platform and come up with the latest techniques to achieve better performance. Prepare and execute the test plan and perform reviews with the cross-functional teams. Collaborate cross functionally with Design, Architecture, Power, Silicon Validation, Performance and SW Teams.

Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM. Create and bring up emulation models for Large Wireless Socs and Display Socs. Port Mixed signal components into emulation models for emulators including Palladium, Protium, Zebu, and Veloce. Write System Verilog or Verilog monitors and checkers. Write System Verilog Assertions for emulation models.

Utilize C-DPI and System Verilog based transactors and monitors for emulation purposes. Understand specifications and create system level Test Plans for emulation verification. Perform Test Plan reviews with Design, Power, Architecture, System and Firmware teams. Create test benches and test cases using System Verilog, UVM and Python script. Automate Test Bench and test cases using Python, Perl.

Run test cases and debug on emulation platforms. Debug and triage failing tests and file bugs, work with design teams to resolve. Analyze regressions by extracting information from splunk databases. Collect coverage and work with designers to close the verification activities. Work with Silicon Validation teams to recreate and debug Silicon Issues.

Work with methodology teams to validate new versions of the tools used in emulation.

40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $142,300 - $214,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

Pay & Benefits

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical, Electrical and Computer Engineering, or related field.

Experience and/or education must include

• Utilizing Verilog/System Verilog to create behavioral models for verification purpose
• Understanding of computer architecture to learn into ASIC/SoC architectures
• Utilizing Scripting tools including Perl, or Python, or Shell to write scripts
• Understanding design of digital logic systems
• Knowledge of ASIC Design and tools for simulation to verify and debug SoC
• Using/applying Design Verification functional coverage for verification closure
• Debugging test failures using logs and waveforms such as Verdi, Indago, or Simvision
• Use of a standard simulation tool such as Cadence’s Xcelium, or Synopsys’s VCS to run simulations
• Applying fundamentals of Digital Design while verifying the SoC design
• Using UVM methodology to create constraint random benches

Preferred Qualifications

N/A